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When using bare-bones busybox-based (64-bit, on RocketChip) Linux, ethernet seems to work the same on both `digilent_nexys_video` and `lambdaconcept_ecpix5`. I can bring up `eth0`, run `udhcpc` to get…
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I follwed VC707 to port KCU105,and modified DDR followed from U250,but without axi_s_ddr_ctrl interface,like this:
![image](https://user-images.githubusercontent.com/64479628/164145525-e8d28310-d4c2…
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I'm building LiteX SoC with Rocket on a digilent nexys video board, which is listed as one of the supported platforms here:
`./litex-boards/litex_boards/targets/digilent_nexys_video.py --sys-clk-fr…
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I have run linux on nexys video follow this repo, Now, I want to debug RISC-V boot。
can you give me some suggestion?
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[mig_b.zip](https://github.com/eugene-tarassov/vivado-risc-v/files/10559866/mig_b.zip)
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified…
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As I always encountered errors when loading firmeare like.
"Error transferring frame: 0x00000000, try pressing the “USB RST” button before loading the bitstream.". with CW310 even though I did press…
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**Describe the bug**
When attempting to build for a Nexys Video board using Linux on LiteX, it claims that this compiler cannot cross-compile for the specified board. This also happens with LiteX sim…
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**Bug Description**
My aim was to replicate the steps taken on the following issues tab https://github.com/litex-hub/linux-on-litex-rocket/issues/29 to boot linux, more specifically `busybox`, onto a…
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Hello there!
I'm building LiteX SoC with a single rocket core on litex_sim using self made dependencies.
The steps taken to build my dependencies are the following:
1. generate the csr file u…
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Compiling [this source](https://github.com/amb5l/tyto2/blob/main/src/common/video_out/video_out_timing.vhd) produces an error during analysis:
```
nvc --std=2008 --work=work -a --relaxed video_out_t…
amb5l updated
2 years ago