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[mig_b.zip](https://github.com/eugene-tarassov/vivado-risc-v/files/10559866/mig_b.zip)
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified…
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As I always encountered errors when loading firmeare like.
"Error transferring frame: 0x00000000, try pressing the “USB RST” button before loading the bitstream.". with CW310 even though I did press…
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**Describe the bug**
When attempting to build for a Nexys Video board using Linux on LiteX, it claims that this compiler cannot cross-compile for the specified board. This also happens with LiteX sim…
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When using bare-bones busybox-based (64-bit, on RocketChip) Linux, ethernet seems to work the same on both `digilent_nexys_video` and `lambdaconcept_ecpix5`. I can bring up `eth0`, run `udhcpc` to get…
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Hello there!
I'm building LiteX SoC with a single rocket core on litex_sim using self made dependencies.
The steps taken to build my dependencies are the following:
1. generate the csr file u…
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**Bug Description**
My aim was to replicate the steps taken on the following issues tab https://github.com/litex-hub/linux-on-litex-rocket/issues/29 to boot linux, more specifically `busybox`, onto a…
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Compiling [this source](https://github.com/amb5l/tyto2/blob/main/src/common/video_out/video_out_timing.vhd) produces an error during analysis:
```
nvc --std=2008 --work=work -a --relaxed video_out_t…
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I'm following [this](https://zipcpu.com/zipcpu/2018/01/31/cpu-build.html) tutorial to build ZipCPU. After installing Verilator from source and the dependencies to build this project, I'm getting an er…
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Windows/MSYS2, NVC commit 71d5882
Enabling waveform output during simulation causes an exception:
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** Note: writing FST waveform data to tb_np6532_poc_128k_digilent_nexys_video.fst
…
amb5l updated
2 years ago
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The CPU reset button on the Nexys Video does not work _until_ the spiflash tools was used. It seems the initial GPIO state of `jtag_srst_n` is driven to 0? As suggested in #1159 this is probably solve…