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Simulate primary input (volt/current) with a SPICE (ngspice) model.
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## SPICE Model refactoring
Is there any intent to refactor the PDK? I suggest to make this a priority before tinkering more with the PDK itself because I observed the following issues.
- The de…
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### Environment (OS, Python version, PySpice version, simulator)
Ubuntu 20.04, Python 3.9.7, PySpice 1.5
### Expected Behaviour
Work with Python Thread for parallel circuit simulation
### …
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INFO worker.py:1544 -- Started a local Ray instance. View the dashboard at [127.0.0.1:8265](http://127.0.0.1:8265/)
INFO algorithm_config.py:2899 -- Your framework setting is 'tf', meaning you are u…
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Hi,
I have tried to get componant value as we can do in ngspice but it does not return anything
Example
a verat basic simple netlist
V0 1 0 5
R1 1 0 100
.tran 0.001 50 uic
Your plug-in giv…
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**Describe the bug**
Trying to run the first example from [pyspice](https://github.com/devbisme/skidl/blob/master/examples/spice-sim-intro/spice-sim-intro.ipynb) and can't find `node`
Core issue m…
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The repository should contain example of how to do a spice simulation of the SRAM macro using common open source tools like xyce / ngspice.
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in the file `IHP-Open-PDK-dev/ihp-sg13g2/libs.tech/ngspice/models/sg13g2_hbt_mod.lib` there is a model:
```
.subckt pnpMPA e b c
.param a=2p p=6u ac=13.33p pc=14.64u
+ dev_a=a*1e12 dev_p=p*1e6 sub…
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In menu Simulation:
![image](https://github.com/ra3xdh/qucs_s/assets/10200568/820db325-5fdb-4d3f-902a-87fdf1b40d59)
Please update the following:
1. "Tune" to _Ajustes_.
2. "Save netlist" to…
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FAILING TESTS
freepdk45/20_psram_1bank_4mux_1rw_1r_test.bad
freepdk45/20_sram_1bank_2mux_1rw_1r_test.bad
freepdk45/20_sram_1bank_2mux_1w_1r_test.bad
freepdk45/20_sram_1bank_2mux_global_test.bad
f…