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Hi the download environment script never goes as far as installing the litex suite because it fails to clone liteusb. Is liteusb no longer a thing? I'm getting a 404 from https://github.com/enjoy-digi…
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### Is there an existing issue?
- [X] I have searched the existing issues
### Experiencing problems? Have you tried our Discord first?
- [X] This is not a support question.
### Motivation
A desir…
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Hi, first of all I'm really glad you made this wrapper as it provides a starting point and reference for a FPGA noob like me to start modifying picosoc verilog codes. Thank you for creating this repo!…
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## Description
This issue is not so much an issue, but a compilation of my findings when researching how to use abc to verify hardware models using PDR. More specifically, what commands to run to b…
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I have been playing with riscv-formal for checking one of our small processors, and I came across a few issues where the documentation does not appear to match what the checks are actually doing. Our …
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Was just checking github for upduino related things, I have a 2.0 :)
There were a lot of complaints on the 1.0, the 2.0 is a lot better, but probably still not prefect.
I think one point of attentio…
ghost updated
4 years ago
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### Describe the bug
Following the suggestion here https://github.com/The-OpenROAD-Project/OpenROAD/discussions/5507#discussioncomment-10250593 on how to run `repair_antennas` after detailed routin…
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In the provided [example](https://github.com/chili-chips-ba/openCologne/tree/main/2.Simple--1--PSRAM) if you change the bit width of `counter` from 6 to any other number the design stops working, UART…
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繳交截止時間：2023/01/8 (週日）23:59 截止
# 1. 電路程式實作與心得閱讀筆記
1. 用 Verilog 重做一次 nand2tetris 的所有習題
2. 用 Verilog 設計一個 RISC-V 處理器
3. 用 Verilog 設計一個自己發明的處理器
4. 用 C/Python/... 自行設計一個 HackCPU / RISC-V 的組譯器或虛擬機
…