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Such as i want to use debug feature of risc-tests during Synopsys VCS or Cadence XRUN simulation?
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Based on the comments in https://github.com/iains/gcc-darwin-arm64/issues/49#issuecomment-972599628, I did a first run to build `riscv-none-embed-gcc`.
For now I applied only the 8 patches I alread…
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Hello,
I am running into problems running make ARCH=riscv. When I run this, I get the console output below:
gcc: error: unrecognized argument in option ‘-mabi=lp64’
gcc: note: valid arguments to …
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I just built all the tools today from latest source code.
I compile my program with C++11 nothing else on ubuntu 18.04.
```
File *file = fopen(filepath, "w")
```
If this file doesn't exist befo…
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According to some forum comments, I check out FreeRTOS branch but find nothing about FreeRTOS. And under V1_0FreeRTOS branch, I cannot pass the compilation.
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Hi all,
I am interested in implementing the rocket core(s) on either the Arty35T or the Arty100T.
However, I would like the core(s) to have access to the 256MB of off-chip memory available on thes…
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I followed this link to do https://github.com/kraj/meta-musl. This link provides the application of musl-libc library set on OpenEmbedded/Yocto.I added the layer to bblayers.conf and also added TCLIBC…
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Hi,
After building the linux-4.18.2 with patching riscv-linux-4.18, BusyBox1.26.2 and initramfs (all steps following to this [README](https://github.com/riscv/riscv-tools/tree/priv-1.10#linuxman)),…
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I have followed to https://github.com/SpinalHDL/VexRiscv/tree/master/doc/nativeJtag, but I need to modify for my Altera DE0-Nano-SoC board (Cyclone® V SE 5CSEMA4U23C6N device) and Altera Virtual JTAG.…