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The file el2_pic_ctrl.sv contains a 4-bit logic called "mask", which is undriven. This results in X data being driven on picm_rd_data_in and subsequently corrupts the contents of internal PIC register…
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Hey I have build the tool-chain using --enable-multilib with installation path /opt/riscv/bin
Now when i run the code using the following command:
/opt/riscv/bin/riscv64-unknown-elf-gcc /home/wale…
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With introduction swerv EH2 processor we need support to generate multithreaded tests.
At least 1 thing must to be supported:
separate data and stack setup per thread to avoid true sharing proble…
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I'm new to this repo, and failed to find the tests signatures, results. I think these were provided at some point .. What do I check/compare with my run results?
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Hi,
I think _lsu_cmpen_dc2_ signal has no importance,
https://github.com/chipsalliance/Cores-SweRV-EH2/blob/a95fdb81ea6dc19239cfe2953ef00710a6f1cf2a/design/lsu/eh2_lsu.sv#L392-L393
Even th…
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cat build/regression/CoresSweRVMP/CoresSweRVMP.log
[INF:CM0023] Creating log file ../../../build/regression/CoresSweRVMP/slpp_unit/surelog.log.
[WRN:CM0010] Command line argument "-Wno-UNOPTFLAT"…
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**Is your feature request related to a problem? Please describe.**
I'm trying to create the correct platform collateral for intel16. I have filled in good candidate cells for the active high and acti…
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While simulating swerv EL2 core (https://github.com/chipsalliance/Cores-SweRV-EL2) and running coreMark test I've noticed that the resulting score differs when running verilator 4.222 vs irun.
Ver…
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If a trigger with `mcontrol.chain=1` matches, but the next trigger does not match, no exception happens.
Should the first trigger's `mcontrol.hit` bit be set in that case?
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Hi,
Can you take a look, please, why GCC dies if we select large BTB structure ( a lot of flops)?
I noticed this too recently. Xrun compiles just fine ..
https://github.com/chipsalliance/Cores-…