chipsalliance riscv-dv issues

chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification

Apache License 2.0

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issues

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Need to check Verible Version in build-verible.sh

#994 Ashwin4514 opened 1 week ago
0
Generation of multi-hart tests with virtual memory enabled

#993 Wlgen opened 2 weeks ago
0
how to regenerate src SV classes after modifying scripts in riscv-dv/pygen/pygen-src/*py

#992 svasekar opened 4 weeks ago
0
Make renode_wrapper more configurable

#991 MateuszKarlic opened 3 months ago
0
Understanding the Role of UVM and Circuit Simulators

#990 mutianzh opened 3 months ago
0
added options and information for siemens questasim simulator support…

#989 ludovicpion opened 4 months ago
1
run: fix disabling the `c` extension

#988 fkokosinski opened 4 months ago
0
Fix CSR test generation for RV64

#987 serge0699 opened 4 months ago
0
Error: illegal operands `sd s11,sub_4_stack_p(s5)'

#986 il-steffen opened 4 months ago
0
updated for python 3.12

#985 5hayanB opened 4 months ago
0
allow specifying privilege modes for simulation

#984 wsipak opened 5 months ago
0
Fix gen_callback

#983 HuashuQ opened 5 months ago
2
Can I run this without install any external library?

#982 kjhhgt76 opened 5 months ago
0
Remove unused local variables and fix gen_callback

#981 HuashuQ closed 5 months ago
2
Fix isa and mabi argument handling

#980 koblonczek opened 6 months ago
0
Can riscv-dv used with ucb rocket core/boom core?

#979 Sai-Manish opened 6 months ago
6
Request for detailed documentation

#978 fangzhigang32 opened 6 months ago
1
Initial mret (from init_supervisor_mode) sends processor to untranslated address

#977 talhashahzad12345 opened 6 months ago
0
Randomize CSR in main

#976 predator-111 opened 7 months ago
6
Can't do S-mode test ( No delegation )

#975 AhmedAmrAbdellatif1 opened 7 months ago
3
Guide lines to enable virtual address translation?

#974 mukesh891 opened 8 months ago
0
How to test Atomic Extension?

#973 AhmedAmrAbdellatif1 opened 8 months ago
3
can't do riscv_csr_test

#972 AhmedAmrAbdellatif1 opened 9 months ago
1
Access Exception error while running spike for rv64imac instructions

#971 omanzoor opened 9 months ago
0
How to connect the test to my SV design file, and How do I get the feedback that the test has passed or failed?

#970 AhmedAmrAbdellatif1 opened 9 months ago
1
Error: illegal operands `sd s11,sub_4_stack_p(s5)'

#969 AhmedAmrAbdellatif1 closed 9 months ago
0
Error: unrecognized opcode `csrr x5,0xf14', extension `zicsr' required

#968 AhmedAmrAbdellatif1 closed 9 months ago
10
Error "SolveBeforeMustBeRand" while Elaborating with Dsim tool

#967 magnetworks opened 9 months ago
2
Circular dependency within source files

#966 yesilzeytin opened 10 months ago
0
spike error：free(): invalid pointer: 0xxxxxxx

#965 Lebattt closed 11 months ago
0
riscv-dv breaks with riscv64-unknown-elf-gcc version tags 2023.04.18 and up

#964 5hayanB opened 1 year ago
5
rv64gc failing spike due to exception trap_store_address_misaligned

#963 kevinhe5 opened 1 year ago
2
The spike simulation gets stuck in an endless loop

#962 riscv1111 opened 1 year ago
2
spike

#961 riscv1111 opened 1 year ago
0
Fix Ctrl-C processing & use as lib with recent python versions

#960 cathales closed 1 year ago
1
ISS usage fixes

#959 mkurc-ant closed 1 year ago
0
use ovpsim .Why is there no verbose log instruction

#958 moyouth opened 1 year ago
5
Instruction Address Misalign Exception

#957 bmverma opened 1 year ago
0
Extend CI matrix

#956 eszpotanski closed 1 year ago
0
Add pyflow test

#955 eszpotanski closed 1 year ago
0
for debug mode, how to modify link.ld to match debug rom enter addr

#954 Van2Jo closed 1 year ago
0
for debug mode, how to modify link.ld to match debug rom enter addr

#953 Van2Jo closed 1 year ago
0
for debug mode, how to modify link.ld to match debug rom enter addr

#952 Van2Jo closed 1 year ago
0
for debug mode, how to modify link.ld to match debug rom enter addr

#951 Van2Jo opened 1 year ago
1
Vcs ci

#950 GPlaczek closed 1 year ago
0
mmode_exception_handler is not considering the instruction misaligned, load address misaligned, store/amo address misaligned

#949 annasaikiran opened 1 year ago
0
Allow the CI to run from any branch and any PR

#948 mkurc-ant closed 1 year ago
0
[pygen] riscv_rand_instr_test run failed

#947 sky1989123 opened 1 year ago
1
pyflow callstack_gen randomize fail

#946 sky1989123 opened 1 year ago
1
how to generate compressed instructions regression test

#945 GMYMingyu closed 1 year ago
3