chipsalliance riscv-dv issues

chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification

Apache License 2.0

978 stars 320 forks source link

issues

Newest

Newest Most commented Recently updated Oldest Least commented Least recently updated

added options and information for siemens questasim simulator support…

#989 ludovicpion opened 1 week ago
1
run: fix disabling the `c` extension

#988 fkokosinski opened 2 weeks ago
0
Fix CSR test generation for RV64

#987 serge0699 opened 2 weeks ago
0
Error: illegal operands `sd s11,sub_4_stack_p(s5)'

#986 il-steffen opened 2 weeks ago
0
updated for python 3.12

#985 5hayanB opened 2 weeks ago
0
allow specifying privilege modes for simulation

#984 wsipak opened 4 weeks ago
0
Fix gen_callback

#983 HuashuQ opened 1 month ago
0
Can I run this without install any external library?

#982 kjhhgt76 opened 1 month ago
0
Remove unused local variables and fix gen_callback

#981 HuashuQ closed 1 month ago
1
Fix isa and mabi argument handling

#980 koblonczek opened 1 month ago
0
Can riscv-dv used with ucb rocket core/boom core?

#979 Sai-Manish opened 2 months ago
2
Request for detailed documentation

#978 fangzhigang32 opened 2 months ago
1
Initial mret (from init_supervisor_mode) sends processor to untranslated address

#977 talhashahzad12345 opened 2 months ago
0
Randomize CSR in main

#976 predator-111 opened 3 months ago
6
Can't do S-mode test ( No delegation )

#975 AhmedAmrAbdellatif1 opened 3 months ago
2
Guide lines to enable virtual address translation?

#974 mukesh891 opened 4 months ago
0
How to test Atomic Extension?

#973 AhmedAmrAbdellatif1 opened 4 months ago
3
can't do riscv_csr_test

#972 AhmedAmrAbdellatif1 opened 4 months ago
1
Access Exception error while running spike for rv64imac instructions

#971 omanzoor opened 5 months ago
0
How to connect the test to my SV design file, and How do I get the feedback that the test has passed or failed?

#970 AhmedAmrAbdellatif1 opened 5 months ago
1
Error: illegal operands `sd s11,sub_4_stack_p(s5)'

#969 AhmedAmrAbdellatif1 closed 5 months ago
0
Error: unrecognized opcode `csrr x5,0xf14', extension `zicsr' required

#968 AhmedAmrAbdellatif1 closed 5 months ago
8
Error "SolveBeforeMustBeRand" while Elaborating with Dsim tool

#967 magnetworks opened 5 months ago
2
Circular dependency within source files

#966 yesilzeytin opened 6 months ago
0
spike error：free(): invalid pointer: 0xxxxxxx

#965 Lebattt closed 7 months ago
0
riscv-dv breaks with riscv64-unknown-elf-gcc version tags 2023.04.18 and up

#964 5hayanB opened 8 months ago
5
rv64gc failing spike due to exception trap_store_address_misaligned

#963 kevinhe5 opened 9 months ago
2
The spike simulation gets stuck in an endless loop

#962 riscv1111 opened 9 months ago
2
spike

#961 riscv1111 opened 9 months ago
0
Fix Ctrl-C processing & use as lib with recent python versions

#960 cathales closed 9 months ago
1
ISS usage fixes

#959 mkurc-ant closed 9 months ago
0
use ovpsim .Why is there no verbose log instruction

#958 moyouth opened 9 months ago
5
Instruction Address Misalign Exception

#957 bmverma opened 10 months ago
0
Extend CI matrix

#956 eszpotanski closed 10 months ago
0
Add pyflow test

#955 eszpotanski closed 10 months ago
0
for debug mode, how to modify link.ld to match debug rom enter addr

#954 Van2Jo closed 10 months ago
0
for debug mode, how to modify link.ld to match debug rom enter addr

#953 Van2Jo closed 10 months ago
0
for debug mode, how to modify link.ld to match debug rom enter addr

#952 Van2Jo closed 10 months ago
0
for debug mode, how to modify link.ld to match debug rom enter addr

#951 Van2Jo opened 10 months ago
1
Vcs ci

#950 GPlaczek closed 10 months ago
0
mmode_exception_handler is not considering the instruction misaligned, load address misaligned, store/amo address misaligned

#949 annasaikiran opened 10 months ago
0
Allow the CI to run from any branch and any PR

#948 mkurc-ant closed 10 months ago
0
[pygen] riscv_rand_instr_test run failed

#947 sky1989123 opened 11 months ago
0
pyflow callstack_gen randomize fail

#946 sky1989123 opened 11 months ago
1
how to generate compressed instructions regression test

#945 GMYMingyu closed 11 months ago
3
Test generation failed for riscv_amo_test

#944 jayasree2411 opened 11 months ago
0
no_load_store switching option

#943 hyperion009 opened 11 months ago
0
RVC Instruction gpr coverage collection omissions for CR/CI/CSS formate

#942 LongStudy opened 11 months ago
0
riscv_csr_test fails at generation

#941 fraret opened 1 year ago
0
use pyflow error: ModuleNotFoundError: No module named 'ucis.ucdb'

#940 Damien-Wu opened 1 year ago
1