chipsalliance Cores-VeeR-EL2 issues

chipsalliance / Cores-VeeR-EL2

VeeR EL2 Core

https://chipsalliance.github.io/Cores-VeeR-EL2/html/index.html

Apache License 2.0

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issues

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resize iccm ecc signals

#204 wsipak opened 9 hours ago
1
remove verible formatter

#203 wsipak opened 10 hours ago
1
Include source code in the dashboard

#202 RRozak opened 12 hours ago
1
[DNM] tools/riscv-dv: add bitmanip tests

#201 fkokosinski opened 1 day ago
0
WIP: Extend coverage tests

#200 kiryk opened 2 days ago
2
tools/riscv-dv: add more PMP tests

#199 fkokosinski opened 3 days ago
3
Render docs in Github Pages

#198 jbylicki opened 4 days ago
9
test specifying privilege modes in simulation in riscv-dv

#197 wsipak opened 1 week ago
1
WIP: Fix linter warnings related to undriven nets

#196 koblonczek opened 1 week ago
2
Test instruction buffer debug override

#195 koblonczek opened 1 week ago
2
Testbench: Fix connections between core and memories

#194 kiryk closed 2 weeks ago
2
tools/riscv-dv: add more PMP tests

#193 fkokosinski closed 2 days ago
15
Prepare for user mode tests

#192 kiryk opened 2 weeks ago
0
Fix Verilator build

#191 RRozak closed 2 weeks ago
2
Remove unused jtag module files

#190 RRozak closed 2 weeks ago
2
Upload artifacts only once

#189 RRozak closed 3 weeks ago
3
Enable lib_ahb_to_axi4 tests

#188 RRozak closed 3 weeks ago
1
User mode support

#187 mkurc-ant closed 12 hours ago
4
Fix constant name in custom veer config for riscv-dv

#186 tmichalak closed 3 weeks ago
1
add a test for user mode

#185 wsipak opened 3 weeks ago
7
CI: Add more files to cache hash calculation

#184 kiryk closed 2 weeks ago
3
CI: Add testlists.yaml to cache hash calculation

#183 tmichalak closed 3 weeks ago
2
Sync code with caliptra-rtl repo

#182 koblonczek closed 2 days ago
2
Show only design dir in the dashboard and enable 'all' coverage in all tests

#181 RRozak closed 3 weeks ago
5
Add tests of zbs and zbb instructions

#180 RRozak closed 4 weeks ago
2
Increase AXI timeout to prevent spontaneous DMA test failures

#179 koblonczek closed 4 weeks ago
1
Fix black and isort not failing CI on incorrect formatting

#178 koblonczek closed 4 weeks ago
1
Add tests of pack and packh instructions

#177 RRozak closed 4 weeks ago
2
tools/riscv-dv: add a separate testlist.yaml

#176 fkokosinski closed 4 weeks ago
6
Add tests of sh??add instructions

#175 RRozak closed 1 month ago
3
Non-functional fixes to exu_alu testbench

#174 RRozak closed 1 month ago
2
Use C++14

#173 kiryk closed 1 month ago
0
Add .dat files to artifacts

#172 RRozak closed 1 month ago
3
Enable all coverage in all tests

#171 RRozak closed 3 weeks ago
2
Add Test-Microarchitectural to Report-Coverage dependencies

#170 RRozak closed 1 month ago
2
EL2_DMA_CTRL.sv AXI interface the burst length mode, awlen & arlen is not used, it is Error ?

#169 xiaolei-cheng opened 1 month ago
0
Relation between Core reset(rst_l) and dbg_rst_l

#168 Syed-mudabbir-ahsan opened 2 months ago
0
Bump Verilator for UVM tests

#167 kbieganski closed 2 months ago
1
Request to review Lint Issues in Veer RTL

#166 amullick007 opened 3 months ago
2
FuseSoC core description file is missing

#165 olofk opened 3 months ago
0
Error while build through "make irun"

#164 ajaysilla closed 1 month ago
7
Does this design work with VCS/Cadence/Mentor simulators after memories were moved from design to tb_top?

#163 algrobman opened 4 months ago
1
Simulation hits max cycle count for dhry, cmark_iccm, cmark_dccm

#162 GeorgeWu1204 closed 4 months ago
11
LHS lesser than RHS : el2_ifu_mem_ctl.sv : ic_debug_way

#161 nstewart-amd opened 4 months ago
0
CDC Error

#160 Syed-mudabbir-ahsan closed 2 months ago
1
Caliptra JTAG TdoEn missing output

#159 nstewart-amd closed 2 days ago
2
UCR in synthesis

#158 Syed-mudabbir-ahsan closed 4 months ago
0
AHB to AXI4 Lite converter tests

#157 mkurc-ant closed 5 months ago
2
Add DMI mux with DMI tests

#156 robertszczepanski closed 5 months ago
2
Deterministic VeeR config

#155 mkurc-ant closed 6 months ago
1