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Hi,
The `verible-verilog-lint` tool detects a syntax error in the wrong line (version v0.0-2492-gd122fac8).
Given the following file (test_preprocessing.sv), the error is in line 4 but it is de…
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## Issue description
On my machine using nixos-unstable the upgrade process does not finish due to following error:
```
/build/kernel/nvidia-uvm/uvm8_tools.c:207:13: error: conflicting types fo…
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### Describe the bug
I have nix-shell with `pytorch` installed in the following way:
```cpp
buildInputs = with pkgs; [
python311
python311Packages.pip
python311Packages.pytorch-bi…
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run python train.py
Total number of training data: 6000
GPU available: True (cuda), used: True
TPU available: False, using: 0 TPU cores
IPU available: False, using: 0 IPUs
HPU available: Fals…
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When I running simulation UVM based, vsim command crashed and tool is killed.
See below the log:
[2021-05-14 12:40:22 EDT] vlib work && vlog -writetoplevels questa.tops '-timescale' '1ns/1ns' +i…
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Compiled : f0f2b60df2ee87b223a2b0dce95e9bed244cc488
with a patchset against master.
Compiles cleanly but Nvidia DRM module (381.22) fails to compile against the target (works fine against 4.11…
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Hi WeiChung,
Thanks for you SystemVerilog plugins, it helps me a lot in implenting verification environment.
I am writing to ask for one enhancement of this plugins for uvm_info sentences.
If w…
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使用npx @dcloudio/uvm为什么会更新到alpha版本，alpha是最新的稳定版本吗
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Tabular alignment is currently not handled by the tool. Below are a couple of test cases for this feature.
## example a)
should:
```systemverilog
rand bit [ADDR_WIDTH-1:0] addr;
rand rw…
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https://wmchappy.cn/2021/01/24/uvm-model/
很早之前就说写一个简单的uvm环境 首先是一个简单的dut 123456789101112131415161718192021222324252627282930`timescale lns/10fsmodule mul( clk, rst_n, num_a, num_b, …