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Encountered the following errors:
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 18.1.0 Build 625 09/12/…
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First of all: Thank you for maintaining this project.
I used a Terasic Development board in first semester but didn't learn Verilog or Altera HDL. Some minor VHDL knowledge is there, but it's not rea…
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Hi,
I am trying to generate the verilog files for the ethernet module from the .py files. I have used the pyverilog though it is giving some errors.
$ ~/Downloads/Pyverilog/eth$ python3 eth_mac.…
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hi,
i am completely new to spinal hdl and vexriscv
and i have knowledge about verilog linux and buildroot
i compiled Linux.scala and simulated linux in verilator and i like it because it is fas…
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It would be helpful if `cocotb.triggers.Timer` could precisely match unit-less verilog delays, which are multiples of the simulator time unit. For instance to write assertions on the value of `q`:
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Objective: bringing back the non-free model user experience, as an optional extension to QUCS.
on the QUCS end
- [x] implement dynamic loader (dlopen)
- [x] implement a dictionary for components
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Tang primer 20k has a working example of the usb3317 being used (https://github.com/sipeed/TangPrimer-20K-example/tree/main/USB).
This example has been generated via https://luna.readthedocs.io/en/l…
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I wrote down two files: Convolution_2x2.py (module), tb_Convolution_2x2.py (testbench)
I want to do below four things in one code **when I execute my testbench code (e.g. Command: python tb_Convolu…
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I think it would be a nice idea to add the possibility to export to HDL from the CLI. It would allow the integration of Digital in Makefile or build scripts.
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The declaration of regs as
```
reg x = 1'b1;
```
such as in https://github.com/efabless/caravel_mgmt_soc_litex/blob/3222bd57445eb6e734f010b9bed369b53c6066fe/verilog/rtl/mgmt_core.v#L150
isn't sup…