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For a 32x16 CGRA (~1MB Verilog file), it takes over 90 seconds to get through the parse step of magma. I really only want the top `Garnet` module's interface to be parsed. My workaround is to just reg…
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I setup `gtest` to handle testing https://github.com/leonardt/verilogAST-cpp, it was really simple to integrate into a cmake based workflow.
Here's some references I used:
* https://github.com/goo…
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Right now, if and when we perform renames for uniquification, the new name is not propagated to instances (it only affects the definition). First this can impact correctness, because if we have differ…
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@jeffsetter I have written a compute unit regression test generator and used it to compare the outputs of the coreir and cpp compute units in isolation for each compute unit in `harris_sch1_onebuf`.
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When multiple producers connect to a single consumer, there needs to be some synchronization between the valid signals. There are issues when they are out-of-sync, as when they have a different valid …
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Hello,
I am afraid that we are doing the exactly the same thing.
https://github.com/Nic30/hwt
https://github.com/Nic30/hwtLib/blob/master/hwtLib/samples/showcase0.py
This library is also S…
Nic30 updated
5 years ago
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Right now, we expect the width of the shift amount to be the same as the width of the value being shifted. This stems from the coreir, hwtypes, and smt interface. The proposal is to support implicit…
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There's already a decorator that does this, see https://github.com/phanrahan/magma/blob/master/magma/circuit.py#L564 but we need to standardize it's use by people writing generators (e.g. in mantle).
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We should review clock wiring. Some circuit definitions call wireclocks and wiredefaultclock, but I am not sure that these are needed. There should be default clock wiring semantics that handles most …
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I changed the init parameter to roms to be a json argument. We should come up with multiple ways to interpret the rom parameter.
I am thinking something like:
{_type: "array", value: [[]]}
or
{_ty…