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Hey so I think I ran into an issue (unless I am interpreting wrong / there is something wrong about the nvim integration)
I have a `(generate_block)` node
![full_generate_block](https://github.c…
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I am trying to run Incisive 15.20 with Vunit but I get syntax errors when compiling the vunit_lib library as shown below:
![vunit_incisive_error_mmsig1](https://user-images.githubusercontent.com/5087…
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**Description**
Got a bug when trying to use generic procedure.
**How to reproduce?**
```vhd :file: mwe.vhd
entity mwe_generic is
generic (
procedure drive_sig (signal s : out bit)…
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**Description**
I've compiled OSVVM libraries using ghdl/synth:formal docker image. Testbenches defined in osvvm/Demo folder works fine with GHDL. Then, I tried AXI4 example of OSVVM. Files pass anal…
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It will be nice to have option to set address separately for read and write. This type of memory widely used in PSX CPU and i can't simulate it via other elements ((
https://en.wikipedia.org/wiki/Dua…
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Could you provide a working example or a command ? I tried to generate simple regex "ab" with test "ab", the out_match has no data after out_valid.
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Hi I am working on adding a new IP to Pulpissimo.
I found this training from this issue.
https://github.com/pulp-platform/pulpissimo/issues/272
Unfortunately, it's one year ago and pulpissimo has…
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I have Created a simulation project in vivado and then exporting that simulation for Questa. To run this simulation using Vunit environment I have created python script. Exported Simulation is creatin…
dsp20 updated
5 years ago
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Hello!
I'm having some troubles in compiling CV32E40X uvm simulation (starting from /sim/uvmt folder) that I've not encountered with CV32E40P.
In particular, using the same simulation enviroment …
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I am currently working with my team on FlooNoC and running the testbenches provided in the FlooNoC examples. We have noticed that all examples are running correctly except for the DMA examples. It see…