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When trying to build the module for an [Allwinner D1 kernel](https://github.com/smaeul/linux/tree/riscv/d1-wip) i get linking errors:
```
LD [M] /home/user/Projects/risc-v-lichee-rv/image_builder…
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I obtained an error in `phase3.py` using the D1-H manual v1.0.
Full log: https://pastebin.com/m7ap8GZP
**Output:**
```bash
# [...]
WARNING:root:'SPI_NDMA_MODE_CTL': Default 17 for field ['7:6…
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## Tip:
`+` add setfeature `-` remove setfeature
e.g.:
Esp32-C3 [RV32IMC]: `-mcpu=baseline_rv32-a-d-f`
Allwinner D1 [RV64GCV]: `-mcpu=baseline_rv64+experimental_v`
## Show builtin
**Co…
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Thought you would like to know that btm 0.6.3 compiles and runs on Risc-V rv64gc
```
root@RVBoards:/tmp/bottom-0.6.3# rustc --version
rustc 1.52.1
root@RVBoards:/tmp/bottom-0.6.3# cargo --versio…
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## error log | 日志或报错信息 | ログ
ncnn/src/layer/riscv/selu_riscv.cpp:47:32: error: 'vmnot_m_b4' was not declared in this scope; did you mean 'vmnor_mm_b4'?
47 | vbool4_t _higher = vmnot_m_…
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I'm using ST7789V display with 4.9.41 Kernel. My DTS file looks like this.
```
&spi1
{
status = "okay";
pinctrl-names = "default";
pinctrl-0 = ;
ti,spi-num-cs = ;
ti,…
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```bash
[root@archlinux ~]# vim /etc/ssh/sshd_config
vim: /usr/lib/libncursesw.so.6: no version information available (required by vim)
vim: /usr/lib/libc.so.6: version `GLIBC_2.33' not found (req…
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Hi! I want to know some information about the execution cycles of the vector instructions.
Does it take more cycles to execute a vector instruction than a scalar instruction?
And does the difference…
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I recently flashed esp-link to a D1 Mini clone and wired it into a consumer product that has an AllWinner R16 SoC and AXP233 PMIC. Everything worked fine out of the box except I had to issue a uC rese…
GMMan updated
4 years ago
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Follow-up for #86
Received request by e-mail from deepsymmetry.org
Pitch values in % :
- -100 -> this stops the incrementing/decrementing
- 0 -> is normal speed
- +100 -> twice the speed…