-
Similar to the issue #722 I am seeing that synthesis is failing
```
Project status:
[S] bitstream: bitstream -> /home/navaneeth/Projects/openmpw/CFU-Playground/soc/build/digilent_arty.proj_…
-
xref: https://github.com/chipsalliance/yosys-f4pga-plugins/pull/485
need to fix https://github.com/chipsalliance/synlig/issues/1961 as well to avoid installing old stuff on Mac build
-
At the moment the user guide is a ODT file in the repo, which is also available as a PDF file on the SourceForge website. From previous issues on GitHub I suspect that some users don't know the user g…
-
It would be awesome to have a better integration of SystemVerilog in openlane2 through the SystemVerilog Plugin for Yosys: https://github.com/chipsalliance/yosys-f4pga-plugins/tree/main/systemverilog-…
-
### Hello everyone!
### Context:
Until now, I synthesized the NEORV32 with *Vivado* and there wasn't any problem. Even I added a module via Stream Link and it worked successfully.
However, I…
-
I am trying to synthesize a module using `Yosys 0.30+16 (git sha1 8b2a00102, gcc 9.3.1 -fPIC -Os)` with the systemverilog plugin from `synlig-plugin-bb5d911-2023-10-02.tar.gz`, but it fails in the `re…
-
Looks like the new function is now called processFormat(). So the systemverilog plug--in will not compile with latest yosys from head as our local copy of `simplify.cc` uses that in [two](https://gith…
-
I hit this case when parsing some advanced Google SystemVerilog with UHDM + Yosys. Not sure what is the exact repro case. I can look into it more if needed, just thought I would flag it ASAP.
line …
-
When running the example, ERROR: TCL interpreter returned an error: couldn't read file _"/home/ankai/desktop/home/opt/f4pga/xc7/conda/envs/xc7/lib/python3.7/site-packages/f4pga /wrappers/tcl/xc7.f4pg…
-
Test bsg_micro_designs/bsg_comm_link/bsg_assembler_out/bsg_assembler_out_num_out_p_5_num_in_p_10_width_p_16/top.v
First merge https://github.com/chipsalliance/Surelog/pull/3502 in the plugin, as th…