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xref: https://github.com/chipsalliance/yosys-f4pga-plugins/pull/485
need to fix https://github.com/chipsalliance/synlig/issues/1961 as well to avoid installing old stuff on Mac build
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At the moment the user guide is a ODT file in the repo, which is also available as a PDF file on the SourceForge website. From previous issues on GitHub I suspect that some users don't know the user g…
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It would be awesome to have a better integration of SystemVerilog in openlane2 through the SystemVerilog Plugin for Yosys: https://github.com/chipsalliance/yosys-f4pga-plugins/tree/main/systemverilog-…
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Looks like the new function is now called processFormat(). So the systemverilog plug--in will not compile with latest yosys from head as our local copy of `simplify.cc` uses that in [two](https://gith…
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When running the example, ERROR: TCL interpreter returned an error: couldn't read file _"/home/ankai/desktop/home/opt/f4pga/xc7/conda/envs/xc7/lib/python3.7/site-packages/f4pga /wrappers/tcl/xc7.f4pg…
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I hit this case when parsing some advanced Google SystemVerilog with UHDM + Yosys. Not sure what is the exact repro case. I can look into it more if needed, just thought I would flag it ASAP.
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Test bsg_micro_designs/bsg_comm_link/bsg_assembler_out/bsg_assembler_out_num_out_p_5_num_in_p_10_width_p_16/top.v
First merge https://github.com/chipsalliance/Surelog/pull/3502 in the plugin, as th…
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I am trying to synthesize a module using `Yosys 0.30+16 (git sha1 8b2a00102, gcc 9.3.1 -fPIC -Os)` with the systemverilog plugin from `synlig-plugin-bb5d911-2023-10-02.tar.gz`, but it fails in the `re…
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Minimal parsing of commands and responses (limited to just their sizes) must be done on FPGA side in order to properly set status bits that host can use to check whether TPM expects more bytes of comm…
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### Hello everyone!
### Context:
Until now, I synthesized the NEORV32 with *Vivado* and there wasn't any problem. Even I added a module via Stream Link and it worked successfully.
However, I…