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Thanks for sharing this amazing library, this pretty much has everything I need.
I consider myself a beginner in HDL programming, and I find it very hard to use this library.
I need to implement a…
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Hello,
Is there documentation which list out Currently integrated List of IP on FPGA platform or road map for IP integration on FPGA.
Is there any time line to integrate Entropy_src IP on Nexy Vi…
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Hi
Is it possible to use Nexys A7 board instead of Nexys video as target fpga for the opentitan on FPGA?
If yes, could you please hint the procedures to do it.
Thanks a lot.
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I'm tring to use Vivado Block Design to add an IP on Windows, and I see device tree need to be updated first before building bitstream. The issue is that, I used Vivado GUI on Windows to model the …
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Using the latest core and BASIC ROM yields the following behavior: the default sprite mode seems to be full vertical resolution (V400) but poking POKE $D076,0 to disable it does not seem to work.
…
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We have a PC with two network cards, one used for ordinary internet access, second to communicate with external hardware. In WSL2, we can see only one virtual card. Is there any way to access the 2nd …
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Hi I am very confused about the xdc and pinmux table, is there anything wrong ? It seems having discrepancy.
Or, any one who can help me understanding it.
Great thanks.
i2c0_sda | muxed |…
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## The problem:
According to Discord (from Geehaf): https://discord.com/channels/719326990221574164/782757495180361778/939498681936257025
"_The video (taken from Nexys A7 with my phone hence the…
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Hello,
I am trying to use the opentitan I2C IP to control an audio codec chip, ADAU1761, on Genesys 2. I have to configure some related registers as shown below. I have read the i2c.hjson, i2c.sv, di…
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Hello,
I'd like to contribute, and I'm wondering what is currently preventing the RISCV Fedora or Debian ports from working on Rocket. Are there any known issues that prevent it, or does it just fa…