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I have a large vhdl design that uses a few different vhdl packages in multiple locations. I'm having trouble stitching everything together in both the .sby file and my System Verilog testbench. I can'…
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Hi,
I have an error of circular dependency when two architectures use the same entity, and one of them maps to the other one. Attached is a small example testbench where I get this error.
**Descri…
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我是做FPGA开发的工作者,初次体验了最新的这个插件,想给出如下建议以及觉得不错的地方:望采纳
1.我觉得那个architecture功能做的不错 可以看到代码的层次结构图,在开发FPGA的时候不用来回的切换vivado界面,比较不错。
2.代码的颜色高亮有点点问题,关键字和变量常量的显示都是蓝色--这个不太具有突出性,我查看的是你里面的fft代码---可以参照插件 Verilog-HDL/S…
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Thanks a lot for this great project! @alexforencich @rodrigomelo9
I am trying to run the `axi-verilog` designs using `verilator`, however, this library does not seem to be compatible with verilator…
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Hi, I wrote simple modules and I can't access Verilog instance from VHDL top. I have mux4to1 (VHDL) and mux2to1 (Verilog). For example, I want to know d_o value of mux2to1 (with label mux2to1_2).
…
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I am working with the hls4ml, and want to do sth with cataplut, and so glad to watch the repo. But I am newer for Singularity, so
can you share **the Singularity image** containing both Catapult and …
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1. How to run regression inside the axi4Lite_avip project
2. How to check the coverage report and Assertions report.
Running the test cases using different tools like a Questa sim and Synopsys to…
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Under some conditions I'm not quite sure about (but most likely involving interfaces and a class that drives the interface), a runtime error is erroneously triggered.
To reproduce, compile the foll…
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The [PoC-Library](https://github.com/VLSI-EDA/PoC) contains her own:
- source file dependency management
- simulator abstraction layer
- testbench naming scheme
so no high-level `run.py` is need…
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I try to run mean example with questa simulator, however:
```
# Unable to open lib libcocotbfli_modelsim.so (libcocotbfli_modelsim.so: cannot open shared object file: No such file or directory)
# c…
m-kru updated
4 years ago