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@bacam @rmn30 @jrtc27 @billmcspadden-riscv
The question of how to guide the coevolution of Sail and the RISCV model is interesting and important.
I think we should strive to keep both in sync, if …
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# RISC-V from scratch 1: Introduction, toolchain setup, and hello world!
A post that discusses what RISC-V is and why it's important, teaches readers how to install the GNU RISC-V toolchain, and walk…
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Hi Community,
I am trying to build simple helloword program with risc64-unknown-elf-gcc to run on spike emulator.
I compiled risc-gnu-toolchain --with-cmodel-medany. I want to use glibc for my …
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Writing C# modules unlocks a lot of functionality in Renode, however it's very difficult to debug these modules.
For example, in this module:
```cs
using System;
using Antmicro.Renode.Core;
u…
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Feature request: There are many architectural options in RISC-V. Many of them cannot be derived from examining processor state (including CSRs and eventually config ), but must be tested ( try someth…
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I am currently attempting to build RISC-V Cuttlefish following the instructions from [README.md](https://github.com/google/android-riscv64/blob/main/README.md.)
Here is my environment and build com…
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Hello :wave: Cool project!
I just wanted to ask what is planned for the Verilog generation in the TODO section of the README? I'm a Verilog RTL developer and would be keen to contribute to this pro…
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Does the current version support the vector extension?
I try running this:
riscv64-unknown-elf-gcc main.c asm_func.s -o ./a.out -march=rv64gcv
and getting this:
Assembler messages:
Error:…
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I would like to request the addition of Docker support for the following tools:
1. **Spike (RISC-V ISA Simulator)**
2. **RISC-V GNU Toolchain**
3. **riscv-pk (Proxy Kernel)**
If this is po…
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QEMU linux-user emulation has a problem with the `stat` system call on `riscv32`. It is likely that QEMU has the wrong structure. RISC-V is using Linux asm-generic `stat`.
riscv-qemu is using the d…