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Hi,
I was trying to run the PLRAM example in the repo, and ran into some issues when compiling it with v++. When I compile the source directly, as https://github.com/Xilinx/Vitis_Accel_Examples/blo…
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Hi, I'm new about aws fpga and want to try sha on the board.
I'm following the procedures shown here: https://github.com/Xilinx/SDAccel_Examples/tree/2018.2/security/sha1
I've used **_FPGA Devel…
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I can't help but noticing that all examples for host streaming are for Cpp kernels. Is it not possible to achieve the same functionality with OpenCL kernels?
I'm thinking for instance of `host/stre…
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**Describe the bug**
I noticed a problem with the Montecarlo kernel in the dynamic package for all the sizes, when executing on the Xilinx KCU1500 FPGA. There is no error in the compilation, but the …
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Hello,
I have added a bunch of the PyTorch kernels [here](https://gitlab.com/pytorch-complex/vitis_kernels) for Vitis. I was able to get things working using system calls from CMake, but I would a…
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kristopk may suggest to post this issue on AWS forum, but I could not find any discussion on 'create_sdaccel_afi.sh' on the forum.
I tried to make awsxclbin from xclbin using create_sdaccel_afi.sh,…
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Hi, thanks for open-sourcing. I try to compile and run this, after "make all", I got an error bellow:
> LD -o .build_release/lib/libcaffe.so.1.0.0
/usr/bin/ld: cannot find -lxilinxopencl
/usr/bin…
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Following your instructions we are not able to source sdaccel_setup.sh.
It appears that the problem is that sdx is not installed on the aws instance.
We are running a f1.2xlarge aws instance.
The…
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Hello,
I am trying to compile the array_partition example with size modified to 1024x1024 matrix multiplication with Vitis 2020.1 software for Alveo U200 board. I got the following error during the c…
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The example doesn't show what are the input sequences and what is the output sequences. Looks like the code generates two sequences. But I want to give my own input sequences for alignment. How to do …