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我也准备测试一下yolov3在FPGA上的推理,怎么联系沟通一下,我的邮箱 879483813@qq.com
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I'm trying to build a Linux image for a Zybo-Z7-10 board, using your latest (2022-1) bsp and the latest Vivado (2022-2) freshly installed. This results in the following error:
`ERROR: linux-xlnx-5.15…
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We tested the UDP bitrate from the board to the laptop to reach 50Mbps using the command iperf3- c xx.xx.xx.xx - u - b 0.
But on the contrary, the UDP bitrate from the laptop to the development board…
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对于文章中提到的:
“(2)上述操作方法不适用于Zynq系列,原因未知,目前怀疑是某些操作不到位,Zynq系列的单个LUT动态读写,还需要进一步研究。”
有以下方案可以参考
![image](https://user-images.githubusercontent.com/24414582/202851615-007d56b6-f9ae-46ed-9021-046c581c9918.png…
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did you try to create the NVDLA IP for the nv_small with Vivado? If so, how did you manage the connections with the Zynq UltraScale+?
ghost updated
5 years ago
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Hi all,
I'm working with openAMP and zynq.
I'm having issue using peripheral from remote proc (CPI 1) bare metal applciation. In particular seems that TTC0, TTC1 and TTC2 initialization fail.
…
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can i do this project on PYNQ Z2 board?
Can I run this FGPU on FPGA baords with all Zynq-7000 chip?
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## One-Line Summary
The idle kernel does not run automatically after booting after startup kernel has exited.
## Issue Details
### Steps to Reproduce
* Both idle kernel and startup kernel…
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Hi,
I tried all these three branches of this repository to build an image for Xilinx zcu106 board:
mathworks_zynq_R22.1.0
mathworks_zynq_R20.2.1
mathworks_zynq_R19.2.1
I created the folder/…
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Hi, I am working on the ZC706 board with MIG (PL-DDR) enabled in a custom vitis platform.
When using clEnqueueMigrateMemObjects to write buffers, the content of the buffers on the device side are n…