-
Currently we have names which encode details - see https://github.com/SymbiFlow/symbiflow-arch-defs#names
It would be much better if these were described as attributes / parameters inside the pb_ty…
-
## Steps to reproduce the issue
Create the verilog file like;
```verilog
// 4-input, route-through LUT test.
module top( (* keep *) input [3:0] I, output O);
//Cell instances
SB_LUT4…
-
## Steps to reproduce the issue
Running the following verilog file through Yosys;
```verilog
// 4-input LUT test.
module top(input [3:0] I, output O);
always @(I)
case(I)
4'b1…
-
## Assert failure when writing atom_netlist.cleaned.echo.blif
Currently trying to determine if the problem is the eblif or my architecture file. My architecture file works with other blif files.
…
-
Take a look at https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/281
@kc8apf has a WIP change at https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/2235541edfca60…
-
Yosys can output an ["extended" blif format](http://www.clifford.at/yosys/cmd_write_blif.html) which includes a lot of useful extensions which enable BLIF usage for real world FPGA support (related to…
-
In https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/305 we merged a config file for the Probot Autolabeler bot. However, the config references some labels that don't exist;
```yaml…
-
Architecture file -> https://gist.github.com/mithro/ef23fac984eb229a0300bbda22fca6b6
```
tansell@tansell:~/work/catx/testing/vpr-testarch-1$ gdb --args /usr/local/google/home/tansell/work/catx/vtr…
-
When using blocks which have a height > 1, I get the following exception;
```
Program received signal SIGFPE, Arithmetic exception.
0x0000555555bfcd68 in vtr::NdMatrix::operator[] (this=0x555556352…
-
## Steps to reproduce the issue
I was trying to run the following command;
```
yosys -p "synth; abc -lut 4; opt_clean; write_blif -attr -cname -conn -impltf -param build/testarch/2x4/vlut.eblif" …