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Started messing around with CXXRTL today and
could not seem to get yosys to finish emitting CXXRTL.
I was trying to emit CXXRTL from a multi-domain nMIgen
as found here:
https://github.com/Brac…
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Still haven't narrowed this one down to a reproducer that's all that useful:
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-July/008506.html
used revisions:
nmigen : 30e2f91176edcd1c…
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Simulator-only signals (not used in any Module) are useful to me for communicating between parallel processes, say between a main driver and a passive process simulating a RTL module.
They are also…
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### Type of Issues (Question)
Question
### Operating System
Win10 x64 V2004
### Python version
3.8.5 (tags/v3.8.5:580fbb0, Jul 20 2020, 15:57:54) [MSC v.1924 64 bit (AMD64)]```
### PySimpleGUI…
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This "minimal" example is kind of long, but you said you[Whitequark] think you know what buy we're hitting.
I'll keep this example as is for now and try to trim it later.
```python3
"""Simple e…
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I'm using nmigen commit 69ed4918b8b9fc8617064bbfacb92feb720006f2
I expect nmigen to behave more like most other programming languages in that when converting from a smaller RHS type to a larger LHS…
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Take a module with a positive and a negative sensitive clock edge and excite it with pysim. When changing from `Tick('sync_neg')` to `Tick('sync')` the expected half cycle is added, but after a consec…
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Platform example ( simplified version of _blinky ) , fails to simulate. Minimal example of fail
https://github.com/zignig/tinybx_stuff/blob/master/sim_fail/sim_fail.py
Looks to be the clock bind…
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I was copy-pasting from various tutorials and examples, and managed to set up pysim without a clock. This caused `Tick()` to never return. Example snippet
```python
sim = Simulator(spr)
def testb…
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When I run demo exp_inverse.py , the error occurs: Segmentation fault (core dumped)
I found the error comes from `arcsim.init_physics(out_path+'/conf.json', out_path+'/out%d'%epoch,False)`
What shou…