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Perhaps I missed it but does the privileged specification explicitly state that an implementation must implement user (or supervisor) mode in order for the CSRs in the user (or supervisor) space (bits…
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I have been unsuccessful at generating any test in the base test list other than the 'riscv_arithmetic_basic_test'. Most of the test that I try get a CRITICAL issue in the log file and cause the progr…
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I'm attempting to build the U2+L firmware for the first time and it fails with the following errors:
```
Compiling tasks.c
../../../../software/FreeRTOS/Source/tasks.c: Assembler messages:
../..…
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What is the required RISC-V toolchain for this project and where can it be downloaded/Installed? Is this standard riscv-gnu-toolchain or should be something else?
`riscv32-unknown-elf-gcc`
`riscv3…
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**Type of issue**: feature request | question
**Impact**: rtl refactoring | new rtl | unknown
**Development Phase**: request
BOOM currently does not support a 32-bit FPU and thus s…
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We found some inconsistent behavior between ilp32 and ilp32e, according spec it should be same behavior.
We have two options:
- Update ABI spec, describe this difference.
- Fix GCC before GCC 9 r…
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Make fails when run with Coq 8.11.1. The output is as follows: `$make`
```
Generating Makefile
make -f Makefile.coq.all
make[1]: Entering directory '/home/vaishnavi/kami'
COQDEP VFILES
COQC Ka…
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Currently, the softcore has to pass the ebreak complience test, but I don't see any sense in this for a softcore which only implement the machine mode / without linux.
Also, it has the side effect …
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I was trying to test the MXL feature on forvis. I think I found a few issues in that:
1. When running forvis with the --RV64 flag, if I change the MISA.MXL field from 2 (default reset value) to 1 t…