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This is a proposal for a new testers API, and supersedes issues #551 and #547. Nothing is currently set in stone, and feedback from the general Chisel community is desired. So please give it a read an…
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Dear Maintainers,
Thanks for providing svlint (and sv-parser). The following piece of example code should be valid systemverilog from my understanding (ignore that the functionality does not make sen…
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Not sure where else to put this, but I was actually interested in this exact same concept, and there isn't really anything on the 'net about this. Do you have any interest in working on this project?
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Have you seen VUNIT [https://github.com/VUnit/vunit](url)? This might be an interesting integration. It even has file dependency processing.
_Originally posted by @leftink in https://github.com/c…
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When running the above-mentioned example, uvm_fatal is thrown. Looks like APB monitor does not register any items during simulation.
Commands to reproduce the issue:
```
cd test/examples/simple/r…
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Verilator does not allow DPI-C imported tasks cannot pass simulation time, else they get deadlocked as per this issue: #4225, unlike other simulators (Vivado xsim...).
### My use case:
I am buildi…
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Tried this in release 3.7 on Ultimate II, 3.10a on Ultimate 64 Elite and 3.10e on Ultimate II+L:
Using Commodore MPS, Epson FX-80/JX-80, IBM Graphics or IBM Proprinter emulations, once a printed li…
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Greetings !
Awesome project BTW!
I did a quick pilot in my company using PeakRDL with Synopsys VCS, replacing an existing register module with SystemRDL specification + PeakRDL output. Worked Nice…
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**Note: This is a DV/simulation-only clone of a SiVal test tracked in https://github.com/lowRISC/opentitan/issues/20635.**
### Test point
https://github.com/lowRISC/opentitan/blob/d161dede9cfb98…
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Hi, I am trying to synthesis a systemverilog design with synlig (https://github.com/dpetrisko/tt07-dll/tree/main). With the plugin installed from main, the design is able to parse and synthesize to co…