SystemRDL PeakRDL-regblock issues

SystemRDL / PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

http://peakrdl-regblock.readthedocs.io

GNU General Public License v3.0

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issues

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[QUESTION] Self-clearing regblock reset

#123 philipaxer opened 1 week ago
0
[FEATURE]Reduce the CPU_IF logic, use only AXI LITE

#122 roybod opened 2 weeks ago
0
VHDL Field Logic

#121 darsor closed 2 weeks ago
1
[BUG] intr field can miss events during SW writes

#120 hughjackson opened 1 month ago
1
[FEATURE] AHB interface support

#119 Blebowski opened 1 month ago
3
[BUG] software read-only, hardware write-only not working with write enable

#118 miguel9554 opened 2 months ago
0
Fix spyglass warning and add options

#117 mmk-sc opened 3 months ago
0
[BUG] Incorred bit extraction on external component address assignment

#116 apstrike opened 3 months ago
0
[BUG] reg after external mem is only generated if not in regfile or addrmap

#115 paul-demo opened 4 months ago
0
Saturating counters perform inequality check twice in generated logic

#114 paul-demo opened 5 months ago
0
[BUG] Genus unsynthesizable error on rising/falling edge interrupt field

#113 BertVerrycken opened 5 months ago
0
[FEATURE] Parameters in regblock package

#112 benoitdenkinger opened 5 months ago
0
External registers packed struct

#111 benoitdenkinger opened 5 months ago
1
[BUG] memory size is not calulated correctly

#110 arnonsha opened 5 months ago
4
[FEATURE] External register fields

#109 benoitdenkinger closed 5 months ago
1
src: Deduplicate read enable generation.

#108 Blebowski closed 6 months ago
4
Сpuif error response, when the address is decoded incorrectly

#107 3FoH9l opened 6 months ago
0
Fine-grained access rights

#106 Blebowski closed 6 months ago
2
Parity on R/W registers

#105 Blebowski closed 6 months ago
2
Put pragmas around assertions

#104 Blebowski opened 6 months ago
2
More optimized readback stage RTL generation

#103 Blebowski opened 6 months ago
4
Clock gating support

#102 Blebowski opened 6 months ago
4
Unaligned external addressable components

#101 maltaisn opened 6 months ago
0
Interface data width vs register width vs access width

#100 jscheid-ventana opened 6 months ago
1
hwset on multibit field

#99 darrylring opened 7 months ago
5
Allow for WE/WEL in sticky/stickybit fields

#98 mtdudek opened 7 months ago
3
External mem state machine gets confused by rd_ack that may result from READ_FIRST BRAMs

#97 paul-demo closed 6 months ago
3
Timing of swmod seems 1 cycle too early

#96 paul-demo closed 7 months ago
2
Files generated by this project do not work with Verilator

#95 paul-demo closed 7 months ago
3
SW = rw, HW = rw behavior seems incorrect

#94 paul-demo closed 7 months ago
3
unconditional is None # Can only have one unconditional assignment per field

#93 xachb opened 7 months ago
2
Casting For-Loop Iterator to Match Address Width in Decoding Logic

#92 leolitenstorrent opened 7 months ago
0
Request to change from typdef enum int to typedef enum logic to resolve Lint Issues.

#91 amullick007 closed 7 months ago
5
infer accesswidth when only external components in RDL

#90 saberxt opened 7 months ago
4
make field_logic.get_next_q_identifier register independent of reset

#89 aszakacs opened 7 months ago
2
Fix `regwidth` & `accesswidth` on buffer triggers when trigger is a `RegNode`

#88 apstrike closed 7 months ago
1
Spyglass issues with PeakRDL's CSR generated RTL

#87 NajamKhalil closed 7 months ago
10
fix: a typo in SV template

#86 motchy869 closed 8 months ago
0
Support for iverilog

#85 shareefj closed 9 months ago
4
External register fields in structs

#84 mpriestleyidex closed 7 months ago
3
Issue: Error in RegblockExporter.export regarding buffer_writes

#83 xcfuisnewhere closed 9 months ago
4
Bus AMBA APB3 and APB4 have PENABLE signal, but there isn't usage of it in RTL generation file (regblock)

#82 AaronPham0701 closed 9 months ago
7
Cpuif properties

#81 RasmusGOlsen opened 10 months ago
0
Add support for CPUIFs to have parameters

#80 hughjackson closed 7 months ago
2
missing we property in struct register defenition

#79 nirb82 closed 10 months ago
0
Change SV sturcts to packed

#78 UniDanny closed 10 months ago
0
User defined property for specifying cpuif

#77 RasmusGOlsen opened 11 months ago
1
Raising an error for unauthorized read or write

#76 imerkado91 opened 11 months ago
6
Intel Quartus support

#75 eruanno123 closed 10 months ago
1
bug: Incorrect RTL for async reset when field does not have a reset value.

#74 jahagirdar closed 12 months ago
0