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It looks like many of the test models in the "jasper_library/test_models" directory have not been updated in 5 years.
In particular, some of them refer to scripts / black boxes that I am not able …
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Hello, I am attempting to configure a NOC within Firesim version 1.18.0 by utilizing rerocc, with a configuration featuring 5 Rocket cores and 10 Gemmini accelerators. Despite having successfully gene…
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Clean install v1.3
And after create ml-suite conda envrionment, when running python -c "import caffe" it reports the above error.
Any comments?
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After the latest commit to `ip_eth_tx_64.v` (`9b5a8cf24aeeeee9d0eadabb3136f7e7722544e2`), the MyHDL testbench hangs indefinitely:
![image](https://github.com/alexforencich/verilog-ethernet/assets/612…
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When we use the JTAG programmer to download the fpga.bit file to the Alveo u50, the server will automatically restart. After restarting, the lspci will not be able to locate the board, and the blue li…
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Hi.
I saw your interesting projects on the Innova2 - and wanted to ask you:
Have you used the Innova2 FPGA to control the network chip's (ConnectX-5) ingress/egress packets?
I want to hack some…
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This issue concerns the branch to resolve issue 196: https://github.com/Xilinx/ACCL/tree/196-reduceallreduce-issues-on-cyt_rdma
Gather sometimes switches up the output of the first rank and the sec…
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Hi, may I know if two-stage detector model such as Faster RCNN trained with PyTorch is supported currently in Vitis-AI 3.0? If not, then are there any plans for it?
Thank You!
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We are running `make` under `..../corundum/fpga/mqnic/AU50/fpga_100g`, the board package for au50 is installed and our vivado version is 2022.2, whith SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022,…