-
Confession: I'm not sure if this is been a long-standing problem we've been working around before or if there's an oversight on my part, but:
* OpenROAD e036ecf
```
OpenROAD e036ecfaca4bc0efe88a5…
-
I was trying to do a monte carlo simulation so I selected corner mc, while I found sky130_fd_pr__pnp_05v5_W3p40L3p40 is not included.
Below is my .spice codes.
```
*Title: test mc include sky130…
-
Hi. Your repo mentions that for most of the devices are verified by "semi-automatic". Does that include automated LVS scripts that extract resistor/capacitor devices? It seems that I am unable to fin…
-
## Expected Behavior
`make timing` generates liberty headers and creates the liberty libraries (as it does in the sky130 open PDK)
## Actual Behavior
There is no `make timing`, and there are no l…
-
Hi Stefan, I'm just wondering if there's a way to know or generate a spice report to see what the region of operations of your transistors in your respective design? Thanks!
-
### Description
Output ports of such cells have no function and gets rejected by yosys unless the cells are blackboxed.
### Expected Behavior
Cells shouldn't be rejected by yosys
### Envir…
-
## Expected Behavior
Line 16 should read
`* include "sky130_fd_pr__esd_nfet_05v0_nvt.pm3"`
## Actual Behavior
Line 16 now is:
`include "sky130_fd_pr__esd_nfet_05v0_nvt.pm3"`
Because of leadi…
holvo updated
7 months ago
-
Seen on `slot-012` of chipignite `2206q_b`.
- Lower levels do not have text or pins.
- nwell is extracted as connected to `#m4_x_y` (autogenerated name) at level 3 (not a port).
- Level 2 has no…
-
There should be Makefile targets for each `.lib` that needs to be generated.
For example - `make libraries/sky130_fd_sc_ms/v0.0.2/timing/sky130_fd_sc_ms__ff_n40C_1v95.lib` should work.
Currently…
-
https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_pr/tree/main/cells currently only seem to contains klayout and xschem pcells.
In comparison the sky130 repo has a lot more:
https://g…