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Implement all the necessary verilog blocks in order to achieve the digital signal processing in the FPGA as :
- denoising
- demodulation
- decimation
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The fractional octave filters output is squared and heavily low-passed (from 25 ms to 1s response time, sampled at 25 ms), so the decimation factor is of the order of 1000.
Consequently, we can use a…
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Given a depth map, follow the paper's recommendation to generate 3 different levels of resolution. Sounds like they first average and then subsample at half the resolution at each level if decimation.…
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Getting the following error bellow when attempting to run extractor with RTL-SDR. i have un-commented the 'device_args' line in the examples/rtl-sdr file. Not sure where else to look to troubleshoot??…
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Even if the new name seems valid a popup saying that a special character cannot be used.
The DMA block renames correctly but not the 'Decimation of' channel.
Before renaming :
![image](https://us…
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I encountered this issue when trying to run OpenWebRX on an Odroid-U3. When running at a sample rate of 0.25 Msps everything works fine, while at a sample rate of 2.048 Msps the audio would drop out, …
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The issue arises when applying the mesh decimation in Unity.
Currently, the preview system for decimating meshes adds the same preview material to all sub-meshes of the object in order to visualiz…
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In GitLab by @alexxcons on Feb 1, 2019, 10:58
Error before is constant 0.1 ... afterwards it is a wild up and down.
Check if that is correct. ( Put Strewaming Sink before and after filter block to r…
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If I understood correctly based on [a forum post](https://community.home-assistant.io/t/under-new-management-interactive-history-explorer-custom-card/369450/1010), this card might use chart.js to rend…
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