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while running the command ```make gateware``` got this error
![image](https://user-images.githubusercontent.com/61948628/148894003-feb4c789-fbb4-4862-92e6-2eb60951218d.png)
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Hi all,
The HWPE behavior between simulation and FPGA is different. I've tried it with pulp_soc v2.1.0, v3.0.0 and v3.0.1. They all show the same problematic behavior so far.
**INFO:** I'm using…
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I run
```
cascade --march de10 -e share/cascade/test/benchmark/bitcoin/run_25.v --enable_info --profile 3
```
but it runs on CPU.
In ```De10Compiler::compile``` ```De10Compiler::block_on_compile…
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The directory at https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu has;
- blackparrot
- cv32e40p
- lm32
- microwatt
- minerva
- mor1kx
- picorv32
- rocket
- serv…
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I tried to run a simulation of `femtorv32_quark.v` using the Vivado simulator, because I my SoC gets past synthesis well, but gets minimized to nothing during implementation, I do not know what is goi…
jeras updated
2 years ago
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I was wondering if it's possible to make the DE10-Standard programmable via OpenCL using Quartus 19.1 using this repo?
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It seems current open source FPGA dev tool kits are a bit long winded to setup and coming from a Linux sysadmin / devops background the aim would be to have all build environments use docker container…
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Hello,
I was looking for some instructions to recompile modified NVDLA RTL and integrate it into firesim.
Below is my high level understanding:
1. Compile the RTL and generate a new AFI on AWS …
ramcn updated
4 years ago
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Hi @thinkoco
Could you tell me how can create De1-SoC linux image with OpenCL driver and init_opencl_.sh file? I have spent a lot of time looking for any documents about it but i couldn't find anyth…
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