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I am trying to speed-up GDS stream out, therefore I'm comparing two merge attempts:
1. merge using addpath, thereby using .mag files
```
lef read $::env(CONDA_PREFIX)/share/pdk/gf180mcuC/libs.ref/g…
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## Expected Behavior
For a MOSFET, when m=2 is specified in the SPICE Netlist, the drain current in saturation must be almost twice compared to m=1
In the given SPICE netlist I(VD2) must be twice I(…
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https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_pr/issues/80
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### Description
Hello everyone,
I am trying to read verilog file (netlist) using openroad app. I have followed following steps:
1) read_liberty pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liber…
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In our design there are D flipflops and fifo registers. After synthesing yosys , renames the flip flops
sky130_fd_sc_hd_dfrtp_2 _14258 (
.CLK(CLK),
.D(00157),
.Q(mv_output[20]),
.RESET_B(RST_N)
…
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### Description
Good morning,
I am trying to run the OpenLANE flow on my design. There is an error in detailed routing step. There was no error when set::env(FP_PDN_CORE_RING) {0}. When I set ::env(…
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### Description
Hello everyone,
I am new to OpenLane and I am trying to read LEF and DEF files using OpenLane. After using command read_lef, the LEF file is not getting read by the tool. Please sug…
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### Description
I am running placement and routing for a design using OpenLane. The flow is getting completed but i am getting violations such as "max slew, max cap and max fanout". To reduce the vio…
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### Describe the bug
gf180mcuC flow in OpenLane is quitting during `analyze_power_grid`. This is new behavior.
### Expected Behavior
Voltage is not explicitly set. However we didn't run into …
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