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### Describe the bug
gf180mcuC flow in OpenLane is quitting during `analyze_power_grid`. This is new behavior.
### Expected Behavior
Voltage is not explicitly set. However we didn't run into …
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### Description
Hello,
I've recently updated openlane2 to the latest available version as of 2nd december 2023.
I can run the classic flow on any design, but I keep getting the warnings below
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When trying to build `gf18mcu` using `--with-reference` option, I get the following error.
```
(cd gf180mcu && make -j all)
make[1]: Entering directory '/home/karim/work/pdk/volare/gf180mcu/build/…
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The `GF180MCU` PDK has the SpacingRange features (?) in its `techlef` file. It would be good for the OpenROAD tooling to support this.
See report from @kareefardi @ https://github.com/RTimothyEdwar…
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Test design (run `run.sh`):
[drc_memory_gf180.zip](https://github.com/KLayout/klayout/files/10056991/drc_memory_gf180.zip)
Memory usage gradually increases to 60+GB over the course of the checks,…
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### Description
I am running placement and routing for a design using OpenLane. The flow is getting completed but i am getting violations such as "max slew, max cap and max fanout". To reduce the vio…
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I am currently re-implementing caravel using a hierarchy of (padframe + core_chip).
The issue is that I am unable to re-implement the mgmt_protect (as a macro of flattened) without buffering the use…
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We moved the DRC and LVS implementation to:
https://github.com/efabless/globalfoundries-pdk-libs-gf180mcu_fd_pv
We will remove them from PR repo.
@mkkassem @RTimothyEdwards @proppy @marwaneltou…
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### Description
[STEP 10]
[INFO]: Running Placement Resizer Design Optimizations (log: ../home/philipp/libresilicon/StdCellLib/Catalog/gf180_stdcelllib_1/openlane/user_proj_example/runs/22_12_05_08_…