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麻烦比较下。
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[here](https://hackage.haskell.org/package/clash-systemverilog)
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I apologize if this is "operator error" on my part - but I do think I am using this extension as intended. And yes, I did read the manual.
If I set line number setting to No, then no line numbers p…
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Hello, please forgive me for asking such a basic question. I have your extension installed along with the latest version of universal ctags. I have added the path to the executable in the settings a…
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**Is your feature request related to a problem? Please describe.**
I am debugging a system which obviously contains state-machines as *A State Machine is worth a thousand Equations*
GHDL does not e…
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**Describe the bug**
iverilog linter does not work on macos with vscode 1.76.2
**Environment (please complete the following information):**
- OS: macOS 13.2.1
- Chip: Apple silicon M1 pro
- V…
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The application generates this code:
```python
crcOut[0].next = crcIn[5] ^ crcIn[7] ^ crcIn[8] ^ crcIn[9] ^ data[5] ^ data[7] ^ data[8] ^ data[9]
```
but it must be:
```python
cr…
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A couple of questions first
- Your IDE/editor (e.g. vscode, emacs,...) you use with verible LSP ?
vscode
- IDE version: 1-65-1
- What other SystemVerilog plugins are active alongside ?
…
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Currently we use two separate `Clock dom` arguments to represent differential clock inputs (see [clockWizardDifferential](https://hackage.haskell.org/package/clash-prelude-1.6.4/docs/Clash-Xilinx-Cloc…