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When you uncomment,
```systemverilog
// This one doesn't work
// typedef union packed {
// foo_flags::common_flags_t [3:0][7:0] atype_t;
// padded_fooes_t [3:0][7:0] btype_t;
// } top_f…
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I have installed Symbiflow following the instructions at https://f4pga-examples.readthedocs.io/en/latest/getting.html
With the conda environment active, I installed LiteX using the litex_setup.py s…
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When running `conda env create -f $FPGA_FAM/environment.yml` I get the following error:
`Collecting package metadata (repodata.json): done
Solving environment: done
Downloading and Extracting Pac…
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I found that the kintex7'dbs exist in prjxray-db,however symbiflow's cmakelist didn't use kintex7? whether the reason is the loss of primitives in some IP source such as iob18(in the dir of xc/common/…
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The F4PGA workgroup should have its website, https://www.f4pga.org listed
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The new website was briefly using a LF template to showcase them (i.e. https://landscape.cncf.io/card-mode?project=graduated, which pulls data from repo - [displays information](https://landscape.cncf…
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If I read this verilog with UHDM + Yosys and write to verilog I get a different value than the packed struct parameter.
```
package my_package;
typedef struct packed {
logic a;
logi…
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For example, ```VpiListener``` has a lot of methods. Is documentation available?
For example, the ```enterPort``` overridable function passes the ```port``` object. object->VpiSize()=0, object->Vpi…
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Building digilent_arty.py with `--toolchain vivado` succeeds, but when built with `--toolchain f4pga` the build fails with the following error:
```
Found constant-zero generator '$abc$82080$auto$b…
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We need to clean up and reboot the workgroups. Since subworkgroups were an informal concept that is not reflected in our bylaws/charter, let's skip them (SystemVerilog, RISC-V DV) for now so that they…