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### Steps to reproduce the issue:
Consider the following verilog code.
```
module demo (output y);
assign y = 0;
endmodule
```
when synthesized using
```
yosys -p 'synth_ice40 -blif demo…
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The current output format of the timing report showing the critical path can be improved in terms of clarity.
### Issues with current output format
* A lot of information is written multiple tim…
bl0x updated
11 months ago
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If I build for Arty, like this:
```
make PLATFORM=common_soc TARGET=digilent_arty bitstream
```
the timing check for Vivado is not done. Timing failures are ignored. I really want them to be r…
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I'm looking to spool up teaching and turnkey starter kits of getting your feet wet in FPGA and my board of choice is the Sipeed Tang Nano, supported by the Apicula interface layer.
If you could add …
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The SymbiFlow project is trying to improve the performance of the various open source FPGA tooling and hence has a project called "FPGA Tool Perf", see;
* https://j.mp/fpga-tool-perf-spec
* https:…
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The Lattice CrossLink-NX VIP board has two S27KS0641DPBHI020 HyperRAM chips on it; it would be nice to support them.
It looks like, by coincidence or purpose, one of the two chips is wired in such …
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Hello @cliffordwolf ,
I would like to express my sincere thanks to (yosys, picovr, nextpnr, ...) :) It's a lot of fun.
One question! I have modified firmware.c and i inserted static vars but t…
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Hello,
I've a lot of issues with the SRAM example with the io constraints like `sram_addr_to_pad` not known.
When I try to change it to `ADR` in the file `sram_io_ice40`, I've got an error:
`ch…
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This has been an issue I've discussed with @eddiehung for a while, but I want to file it publicly so people can submit testcases for us to work through.
Essentially, the problem is that ABC9 - whic…
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thanks a lot for this extension and the tutorials around the tang nano 9k ! its been super helpful getting started with fpga stuff for me.
im now trying to program a [icesugar-nano](https://github.…