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https://github.com/RTimothyEdwards/open_pdks/blob/cc82b606c3f50baedfcbd99567652e828739ff41/sky130/custom/sky130_fd_io/spice/sky130_fd_io.spice#L2913
Answer appears to be: depends which kinda SPICE …
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https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_pr/tree/main/cells currently only seem to contains klayout and xschem pcells.
In comparison the sky130 repo has a lot more:
https://g…
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Hello,
I've been trying to use the notebooks, and I came across this strange error at Step 6 of the OpenLane flow:
```red
[INFO]: Reading ODB at '/content/runs/RUN_2023.06.17_19.13.55/tmp/floor…
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I needed to simulate the gate level netlist for DFFRAM, but I found that no combination of defines results in functional results with icarus verilog and sky130_fd_sc_hd.v as installed by Open_PDK. De…
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@mithro : All of the verilog files in sky130_fd_sc_hs are making calls to primitives with the wrong names and paths. For example:
`include "../u_dl_p_pg/sky130_fd_sc_hs__u_dl_p_pg.v
sky130_fd_s…
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In `pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v` line number `49162`, there appears to be a syntax error on the line. See the code below. It has an invalid label (should have been …
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I can't think of a use case where we'd want black boxes to be flattened out of existence.
However, in the pre-compare name check, if a black box doesn't exist in one of the circuits, the other one …
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Hi I am trying to run a 16kbyte SRAM on sky130. Is it normal that it will take couple of weeks to generate?
Mine has been running for 1 month now. It generate a temp.gds and I don't see any errors…
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## Expected Behavior
No DRC error in buf_16 cell.
## Actual Behavior
Magic reports a DRC error for sky130_fd_sc_hd__buf_16.gds.
DRC error is licon.8a: poly overlap of poly contact < 0.08um in …
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Here's the diode parameter extraction from `8.3.404`
```
parameters sky130_fd_pr__diode_pw2nd_05v5 a=area*1e+12 p=pj*1e+06
```
And here's `8.3.405`. You can see that both `a` and `pj` occur twice.…