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@jeffsetter thanks for adding that ROM example!
However I notice that the CPU and coreir implementations differ starting at output 256 when using the identity stream, and that the rom seems to be 8…
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Any ideas what is causing this error? I updated coreir.
```
tests/test_coreir/test_clock_tuple_compile.py ERROR:magma:Input port Foo_inst0.clocks not driven
Def:
Instances:
Foo_inst…
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Since there are so many of these, I thought it might be nice to cobble together a complete-ish list of possibilities for backends with a path to generating FPGA implementations. (More exotic backends …
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I have a new error in rom generation even on the rom-fix branch. Now when I do:
```bash
${COREIR_PATH}/bin/coreir --load_libs commonlib --input camera_pipeline.json --output camera_pipeline.v
```…
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Currently we are treating `i8` as a byte and `i1` as a bit but they are semantically different. I proposed we create a `Word` type. It would be parameterized by width, but said width could be restrict…
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This would make upgrading via pip simple (upgrades coreir automatically, so users don't have to rebuild from source). Should be simple enough on linux (can pull the coreir release .tar.gz), we should …
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Ideally we don't have to compile to serialized json everytime to go from magma to coreir. Can we add a function that returns a coreir object as a compilation (rather than writing to json file)? Then w…
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Right now you can use Python's built-in `reduce` function to generate a reduction tree, however in most cases, you'd rather target coreir's reduce primitive and have the downstream tool handle the syn…
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It looks like there's an issue compiling with `g++ (Ubuntu 7.3.0-27ubuntu1~18.04) 7.3.0`. Using `clang++ 6.0.0-1` instead works fine. I'm able to compile `coreir` with `g++-7`and run the binary with n…
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