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Enums like `enum logic [2:0]` are seen as 32 bit wide types. This is a problem only inside the plugin - yosys converts them to properly sized types in later stages.
Test case:
```systemverilog
mo…
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Test: ./yosys/tests/arch/common/logic.v
The trimmed down version of that test has 3 errors in the plugin code (Visible in the corresponding gate netlist):
```
module top
(
input [0:7] in,
…
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Test yosys/tests/arch/common/fsm.v
The plugin creates a state variable that is 2 bits wide instead of 3
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Test yosys/tests/asicworld/code_tidbits_fsm_using_always.v
The plugin generates parameters that are 32 bit wide where they should be 3 bits wide.
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Test: UHDM-integration-tests/tests/ConstSizes/dut.v
./run_formal_verif.sh test=ConstSizes_dut.v
Smaller test:
module dut (output logic[63:0] a);
assign a = 7698294523898761276;
endmodule
UHD…
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This pull request runs successfully on my local machine,
but fails in the CI, because the added part is not available in the WebPack edition:
https://github.com/f4pga/prjxray/pull/1908
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There was a change in the API of SynthSubset class some time back.
The plugin didn't get updated in this test:
https://github.com/chipsalliance/Surelog/actions/runs/3551926372/jobs/5966501132
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Test yosys/tests/simple_scopes.v
./run_formal_verif.sh test=simple_scopes.v
After fix: https://github.com/chipsalliance/Surelog/pull/3262 and https://github.com/chipsalliance/Surelog/pull/3263
O…
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This issue accumulates various ideas for improvements related to f4pga (CLI tool) that was recently merged (#530).
Please refer to https://f4pga.readthedocs.io/en/latest/f4pga/Usage.html and related …
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Test UHDM-integration-tests/tests/xor_assignment/top.sv
./run_formal_verif.sh test=xor_assignment_top.sv
```
module top(output logic a);
initial begin
a = 1;
a ^= 0;
end
…