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I attempted to synthesize the icoboard design files using the open source toolchain, but arachne-pnr fails with "fatal error: unknown model `$_DFFSR_NPP_"
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Presently can't seem to configure `arachne-pnr` or `yosys` to take in the shown `.sdc` file. With `man arachne-pnr` and `man yosys`, the former has the `-p` flag to take in the `.pcf` file, and while …
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I'm building and testing as many things as I can in the 2019-02-21 Fedora/RISC-V build and hit a build error in arachne-pnr. I haven't yet tried to fix it myself, but a quick look suggests it hasn't …
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Hello! I've still got my BlackIce-II board and am trying to get Clifford Wolf's PicoRV32 running on it. I'm running into some problems with getting next-pnr to create an "hx4k" pathway (I know that th…
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Some of the iCE40 devices have a PLL disabled in certain chip packages. Current git head of Project IceStorm adds this information to the chipdb file.
1K ChipDB file:
```
.extra_cell 6 0 PLL
LOCKED …
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Hi,
I want to convert m .asc file to .blif file before writing it to the a binary.
My .asc is an output from arachne-pnr. That is then used by icepack to convert to binary. Is there any way that b…
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I am attempting to use pins 12 and 21 on the SG48 package as a LVDS input by instantiating SB_IO like this:
```
SB_IO #(
.IO_STANDARD("SB_LVDS_INPUT"),
.PIN_TYPE(6'b000000)
) SB_IO (
.INPUT_C…
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Simplified code like this ...
> module bootloader (
> inout pin_usbp,
> inout pin_usbn,
> ...
> );
> wire usb_p_tx;
> wire usb_n_tx;
> wire usb_p_rx;
> wire usb_n_rx;
> wire …
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I'm just trying to upload the _One LED_ Basic Example on my **TinyFPGA BX** board, but I have this error: `FPGA I/O ports not defined`
Here is the command output log:
```
arachne-pnr -d 8k -P cm8…
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(Originally posted as yosys issue #427)
I think I got to the bottom of this. When a clock is used for a global buffer using something like;
SB_GB_IO BtraceClk0
(
.PACKAGE_PIN(traceClk),
.…
mubes updated
6 years ago