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This code have bch error.
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Currently the INT fuzzers solve for L and R solutions independently. This is caused by different in PIP naming in the INT_L and INT_R segbits.
Example of pips with exact name match:
```
INT_L.…
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Hi
When i try to test the example counter_test of X-ray project inside the board Artix7 35tcsg324-1 i have the following error
-- Parsing `counter.v' using frontend ` -vlog2k' --
ERROR: Can't open…
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In Package2017_2_1.tcl on line 728 (commit 81b232aacc3faff6c41964024de181b81e4493aa) the list of supported families is defined as follows:
set_property supported_families { \
…
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The router map lookahead builds a lookahead table from wires to a particular (arbitrary at the right location) sink. That is OK for most of the architecture we run VTR on, but if an architecture had …
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Could you please add MMCM to the Zynq7 parts? That's half the PLLs on the device, and the more accurate ones, at that. I'd try to do it myself, given that it appears to be nothing more than copying …
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Brad,
I tried using the "::tincr::lib_cells:compatible_with" function, but it does not return a result. I generated the cache on the first call (with an open blank design), but on subsequent calls, t…
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Hi Patrick
You mention:
> Other people have builds that work with Vivado, use theirs...
Is there a particular version you recommend for use with Vivado?
I've tried https://github.com/RHSRese…
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The names of wires in the series-7 FPGA have meaning, for example `SW4BEG0` might mean 'the beginning of a wire which runs south west 4 tiles'.
There is the start of some code here -> https://githu…
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We want to be able to tag specific tile locations with attributes / parameters.
It would be good to enable us to tag locations with things like "this is tile X12Y136"