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canny_edge_detection algorithm simulation and synthesis run without error but c/RTL simulation shows error
Starting C/RTL cosimulation ...
C:/Vivado/2019.1/bin/vivado_hls.bat C:/Users/Admin/AppData/…
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Motivated by the discussion from https://github.com/google/xls/issues/587 with @ted-xie.
Enable HW interface specification in DSLX modules: The interface specification of a parameter in a DSLX func…
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I am currently working on SN1022 and I have programmed the board successfully. What is the next step? How do I connect my smart NIC to the host and the ethernet and send the data for the simple wire p…
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Hello,
In my project I want to receive large amount of AXI4 Stream transactions (to validate my IP Cores).
In my test bench I am receiving data by using axi_stream_slave entity and pop_axi_stream() …
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Do we need monitor and scoreboard in order to get the output ?
and if possible kindly share the final code asap
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In the Spinal lib，I find there is axi4 crossbar,axi4 decode ,Will there be axilite4 crossbar and axilite4decode in lib in the future?
qgzln updated
2 years ago
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**Issue by [jordens](https://github.com/jordens)**
_Friday Sep 20, 2019 at 12:09 GMT_
_Originally opened as https://github.com/m-labs/nmigen/issues/213_
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Develop tooling to help with non-trivia…
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Using the AXI4 Memory component I set up a test that starts a burst that crosses the 4k boundary. This did not cause any error. Is that a check that should be active?
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cocotb==1.6.2
cocotbext-axi==0.1.16
Questa Sim-64 Version 10.7f
Hello,
I published this problem in cocotbext-axi: https://github.com/alexforencich/cocotbext-axi/issues/40
But I've tracked it …
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I haven't simulated this; I have just been looking at your code to see if verilog-ethernet could be a compatible replacement for a similar, lesser version that I wrote and shipped in a previous projec…