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One long-standing issue with the workflow with chisel-testers was that we always re-ran the chisel generator. Ideally, you'd be able to re-run all your unit tests on your top level design. We had some…
grebe updated
5 years ago
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#### Related to Book Reading Platform
- Show different viewpoints of the topic under study
- Browser plugin for quick reference populations, i.e., get bibtex from google scholar, and get refernces…
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The CMake support you've added is great but unfortunately I think it is done in a way that makes it basically impossible to use with any generated code (which is very common in my experience).
For …
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The current test flow takes beyond 10 minutes to complete a single full run mostly because of long execution times in the compressor tree generator. I believe the flow can be sped up, but it may requi…
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Hello Community,
My team is planing to tapout a chipyard based design, and we have a different Clock Scheme from the default chipyard design:
…
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The new `Stage`/`Phase` framework is available with an updated `DependencyAPI` coming in FIRRTL 1.3. This issue covers migrating the existing `freechips.rocketchip.system.Generator` object t…
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Hi,
We have done some modifications on scala files about PEs for our purposes. However, we could not see any difference in the output while testing it with SPIKE. We ran build-spike.sh and setup-pat…
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**Type of issue**: Feature Request
**Is your feature request related to a problem? Please describe.**
I would like a way to inspect the FIRRTL output of my Chisel program's execution to verify…
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**Type of issue**: documentation
**Impact**: no functional change
**Development Phase**: proposal
**Other information**
This is a proposal to add some content to the [BlackBoxes github wik…
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**Type of issue**: Feature Request
**Is your feature request related to a problem? Please describe.**
I think that it will be greater if chisel5 can add parameter function.
In Verilog, it can…