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It should be possible to use ODDRX1F instead of ODDRX2F for the address and command bus, so that these signals can be placed on the top IO bank instead of just the left and right.
This seems like a…
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The README file mentions the following:
```
3. Check out /examples/versa_ecp5_udp_loopback for a good practical example of how to get
started with the Liteeth core solo in an FPGA.
```
I've t…
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It seems that there are three ways in which the ECP5 can reset itself in order to handle multi-boot images:
- VCC, VCCAUX and VCCIO8 rise above their POR thresholds.
- Rising edge on PROGRAMN pin
-…
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Hi There,
I am trying to port your booloader to the above board. After tweaking the board pin constraints file to the new board, and a few other tweaks, I now have the bootloader running when I dow…
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### Version
Yosys 0.46+11 (git sha1 0200a7680, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)
### On which OS did this happen?
Linux
### Reproduction Steps
Minimal reproducible example `SoC.sv`:
…
jmi2k updated
4 weeks ago
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Apio has two commands to verify the code, 'apio lint' and 'apio verify' and this is confusing. I am looking into consolidating both of them into a single 'apio lint', possibly with a flag to achieve …
zapta updated
2 weeks ago
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Bitstream for `nexys4ddr`, `trellisboard`, `ecpix5`, and `versa_ecp5`:
- [nexys4ddr.bit.gz](https://github.com/litex-hub/linux-on-litex-rocket/files/6109386/nexys4ddr.bit.gz)
- [trellisboard.svf.gz]…
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When using `synth_ecp5`, it seems `-abc9` has been turned on by default at some point. However, it looks like something got miscompiled, or abc support is missing somehow, meaning `synth_ecp5` just im…
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The [provided ECP5 example](https://github.com/YosysHQ/prjtrellis/tree/master/examples/ecp5_evn) runs only for a few seconds, and then gets stuck (no more LED movement) as shown in the video below. Te…
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Boards using it:
- [ ] versa_ecp5, versa_ecp5_5g