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both for SEO and for just general details, i think we ought bulk up the front page. i'm thinking we replace the three lines of crap with maybe four areas
(1) HPC -- CUDA, OpenCL, accelerators, perf…
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cover the essential parts of the article.
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**The problem you're addressing (if any)**
There are use cases in Dasharo can help in testing peripheral devices (e.g. FPGA connected over PCIe, accelerators) as part of continues integration proce…
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### Disclaimer
This issue is part of a series that are just recording language design ideas that have come up for Carbon. It isn't necessarily a *good* idea, or one that Carbon should definitely ad…
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Following the spec:
https://spec.oneapi.com/level-zero/latest/core/INTRO.html
Level-zero SPEC also works for spatial architectures.
When looking at the `zeInit` function (https://github.com/o…
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Currently the work-items are either managed by OpenMP on CPU or with an OpenCL with 1 CU and 1 work-item with a software loop nest in it (because it is FPGA friendly).
For other accelerators such a…
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In multiple example designs, the fifo in the requestor may overflow if the TX channel is full. I'm trying to solve this problem and I hope we can have some discussion. Thanks.
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When we use the JTAG programmer to download the fpga.bit file to the Alveo u50, the server will automatically restart. After restarting, the lspci will not be able to locate the board, and the blue li…
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Please:
- [x] Check for duplicate requests.
- [x] Describe your goal, and if possible provide a code snippet with a motivating example.
TVM can generate highly optimized operators. Is it possib…
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Hi,
Thanks for your efforts.
I tried to run through the following path test_benchs/cva5_tb.sv, after creating a questasim makefile. But, I found out a lot of x propagations that failed the simula…