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openhwgroup
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cva5
The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
Apache License 2.0
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Preliminary OS support
#27
CKeilbar
opened
3 weeks ago
0
Add FPU (squashed)
#26
CKeilbar
closed
6 months ago
3
Regarding Simulation of 'make run-example-c-project-verilator' in GitLab for CVA-5
#25
Tanishqgithub
opened
8 months ago
1
Clarification Regarding Simulation of CVA-5 Processor
#24
Tanishqgithub
opened
8 months ago
1
Add FPU
#23
CKeilbar
closed
5 months ago
14
Peripheral Reads do not wait for retiring, can cause state corruption
#22
ramonwirsch
closed
10 months ago
1
State of AMO support
#21
ramonwirsch
opened
11 months ago
2
Interest in Flopoco-based FPU, Instruction invalidation on self-modifying code or Verilator Improvements?
#20
ramonwirsch
opened
11 months ago
4
Interrupts can lead to MEPC inconsistent with register state / actually retired operations or pointing to entirely illegal instructions
#19
ramonwirsch
opened
11 months ago
6
Hardware Setup
#18
leloc0609
opened
1 year ago
0
how to use jtag in AMD FGPA
#17
mola1222
opened
1 year ago
0
Fix invalidation address and non power of 2 fifos
#16
CKeilbar
closed
5 months ago
3
AXI DDR
#15
maheshejs
closed
1 year ago
1
cva5 simulation using questasim
#14
AhmedMostafa98
opened
1 year ago
6
Code cleanups
#13
e-matthews
closed
1 year ago
0
Improvements for competition setup
#12
e-matthews
closed
1 year ago
0
Cache architecture of the previous version (Taiga)
#11
demyana123
opened
1 year ago
3
Cache architecture of the CVA5 processor?
#10
Mohamed1984
opened
1 year ago
3
Fixes potential load/store ordering issue when store queue is full
#9
e-matthews
closed
1 year ago
0
CVA5 university competition branch
#8
e-matthews
closed
1 year ago
0
L2: Move be (i.e. wstrb for AXI) into the data FIFO (Fixes #6)
#7
flmeisel
closed
1 year ago
2
Cached memory interface: AXI wstrb not stable if AW handshake completes first
#6
flmeisel
closed
1 year ago
0
Minor fixes
#5
e-matthews
closed
2 years ago
0
Fetch and Load-Store Interface Refactor and LiteX Support
#4
e-matthews
closed
2 years ago
0
Taiga to CVA5 renaming
#3
e-matthews
closed
2 years ago
0
Physical address space, starting at 0x00 in M Mode, fail at first control flow
#2
c-93
closed
2 years ago
2
Post-transfer Updates
#1
e-matthews
closed
2 years ago
0