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Hello everyone,
I want to know which kind of JTAG debugger is supported on VCU118 board.
Xilinx internal JTAG chain via the bscane2 primitive or external JTAG debugger?
Is any changes needed on fpg…
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### Development Kit
Custom
### Module or chip used
ESP32-WROVER-E
### Debug Adapter
nanoDAP-HS
### OpenOCD version
v0.12.0-esp32-20240318
### Operating System
ArchLinux
### Using an IDE ?
v…
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Hi Guys,
I want to use the USB port as a midi device so I need to get JTAG debugging going over the pins.
Is there any documentation anyway about how to do this, pins to use, fuses to burn etc?
…
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In my country I can only find these JTAG models:
![image](https://github.com/user-attachments/assets/63064d71-980f-4f25-a070-ad6d4bef00c9)
Will any of them work?
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Hello. Thank you for sharing this great project and I have a question for connecting T113-S3 with JTAG.
I used a uSD to JTAG converter board on MangoPi T113-S3 board (MPi-MQ1DW) with a 16MB SPINOR fl…
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Greetings,
I wanted to report an issue I was having using this go package. I recently got some used boards of ebay (claimed they still worked) to practice hacking on and the like. The reason I grab…
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Try to get debugger working with the Xtensa architecture, which requires OpenOCD. Looks like some binaries aren't in the expected directories after following the [directions](https://docs.esp-rs.org/b…
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I'm trying to debug a failure that's showing up in "rv_dm", a small wrapper around the `riscv-dbg` module in OpenTitan. The issue comes up when the JTAG clock is being driven at a higher frequency tha…
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### Before start
- [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。
- [X] I have searched the previous issues and did not find anything releva…
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### Hierarchy of regression failure
Block level
### Failure Description
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:24) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_rese…