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pulp-platform
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riscv-dbg
RISC-V Debug Support for our PULP RISC-V Cores
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length of the index of the progbuf might be wrong?
#176
omerguzelelectronicguy
opened
1 week ago
0
Verilatable jtag_test module
#175
Scheremo
opened
1 week ago
0
Consecutive dtmcs scans after a dmi scan should never result in a busy status
#174
wajahat-ali-khan-96
opened
1 month ago
0
TDO is driven on th rising edge of tck
#173
omerguzelelectronicguy
closed
1 month ago
1
Review of External Debug Security Spec
#172
bcstrongx
opened
2 months ago
0
Critical bug in flow control of dm_csrs
#171
Scheremo
closed
3 months ago
4
Incorrect results when reading too many bits from IDCODE
#170
rswarbrick
closed
4 months ago
2
src: Fix wrong reset state for TAP after trst_ni
#169
bluewww
closed
4 months ago
0
Update Readme
#168
bluewww
closed
4 months ago
0
WIP: Add a simpler version of the driver compatible with Verilator 5.020
#167
thommythomaso
opened
4 months ago
2
Timing of DMI req/rsp signals
#166
rswarbrick
opened
5 months ago
3
Reset state after trst_ni is wrong
#165
bluewww
closed
4 months ago
0
fix bugs for nrharts
#164
LuisDonatien
opened
5 months ago
2
Behaviour when JTAG clock is much faster than the system clock
#163
rswarbrick
opened
5 months ago
4
JTAG_TAP status can't be exited shift_ir, and traped in loop
#162
Lebattt
opened
6 months ago
0
dmcontrol.haltreq should always read as 0
#161
bcstrongx
opened
6 months ago
0
Misc fixes
#160
msfschaffner
closed
5 months ago
1
debug_rom: Fix non-resettable FF
#159
niwis
closed
1 year ago
1
Change default IDCODE
#158
bluewww
closed
1 year ago
0
Simulating with "VCS" and RiscV 64-bit toolchain.
#157
arash-vafaei
closed
1 year ago
1
Release 0.8.0
#156
bluewww
closed
1 year ago
0
dm_csrs: Fix W1C behavior of `sberror`
#155
andreaskurth
closed
1 year ago
1
`sberror` not clearing properly causes OpenOCD interoperability issues
#154
timothytrippel
closed
1 year ago
3
remote bitbang failing on halt command and sampling wrong IR capture
#153
ElectronicBatman
opened
1 year ago
1
Add `xprop_off` to Xprop-incompatible processes
#152
andreaskurth
closed
1 year ago
0
Fix debug ROM generator
#151
andreaskurth
closed
1 year ago
0
Change `unique case inside` to `unique case`
#150
andreaskurth
closed
1 year ago
1
questions about -rtos riscv in dm_compliance_test.cfg
#149
coderalai
opened
1 year ago
1
[Question]: OpenOCD Compliance Support
#148
sajjadahmed677
closed
1 year ago
1
Update CHANGELOG.md
#147
bluewww
closed
2 years ago
0
Misc Testbench Improvements
#146
bluewww
closed
2 years ago
0
[fix] Realign addresses to 64-bit
#145
creinwar
closed
2 years ago
1
[dm_mem] Addressing does not take strobes into account
#144
creinwar
closed
2 years ago
0
Prepare for release
#143
bluewww
closed
2 years ago
0
tb: Fix make vcsify
#142
bluewww
closed
2 years ago
0
Fix testbench build and test scripts
#141
bluewww
closed
2 years ago
0
dm_mem: Clear state of hart upon ndmreset
#140
andreaskurth
closed
2 years ago
0
dmi_jtag_tap: Bring all state to initial value in Test-Logic-Reset
#139
andreaskurth
closed
2 years ago
0
Fix DMI response when command or SBA are busy
#138
andreaskurth
closed
2 years ago
3
Assertion failure expected?
#137
dpetrisko
opened
2 years ago
2
dmi_jtag_tap: Use generic tech cells
#136
colluca
closed
2 years ago
0
Bender issue
#135
AlexChenIHP
closed
2 years ago
0
jtag_test: Add read_dmi_exp_backoff() and sba_read_double() functions
#134
colluca
closed
2 years ago
0
Fix remote_bitbang r/s/t/u-reset command implementations.
#133
epsilon537
closed
2 years ago
0
Port Travis CI to GitHub Actions workflow
#132
harsiddhdave44
closed
1 year ago
2
compile error: can't find module cdc_2phase_clearable
#131
damnsavage
opened
2 years ago
3
Re-align pins of dmi_bscane_tap with dmi_jtag_tap
#130
huettern
closed
2 years ago
0
[dm_sba] Implement SBA bad address error
#129
msfschaffner
closed
2 years ago
3
[sba] Add support for response timeout
#128
sriyerg
opened
2 years ago
0
[dm_csrs] Correct reset value of sbcs register
#127
msfschaffner
closed
2 years ago
0
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