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Hi,
First of all thanks for the great project. I wanted to know the difference between nextpnr-fpga-interchange and nextpnr-xilinx and in which part of the project RapidWright is used. My guess is th…
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I'm using [MakeBlackbox](https://github.com/Xilinx/RapidWright/blob/60a571446d1bb78b9aba6ed497914631c2e7bc97/src/com/xilinx/rapidwright/util/MakeBlackBox.java#L35) in my design following the tutorial …
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I see "getByteOffset" method in rapidwright/javadoc, but I cannot find it when using RapidWright with python.
Is this not implemented yet, or is there something wrong with my environments?
Thank…
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https://github.com/Xilinx/RapidWright/blob/6cf64a84a086fc0e013b372e66814f1a13ca1c4a/src/com/xilinx/rapidwright/util/FileTools.java#L1680-L1683
Would this not mean that new files would not get unpac…
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With the assumption of .route file store the pips's names how to convert f4pag's result into dcp file and generate bit through vivado?
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==============================================================================
== Device Resources Dump: xcvu7p-flvb2104-1-e ==
========================================…
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Hi, @dlmiles , @Kakadu , I'd like to report a vulnerability issue in **com.xilinx.rapidwright:qtjambi-linux64-gcc:4.5.2_01**.
### Issue Description
**com.xilinx.rapidwright:qtjambi-linux64-gcc:4.5.2…
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After the most recent [RapidWright patch](https://github.com/Xilinx/RapidWright/issues/143#issuecomment-808581791) to `getPinMappingsP2L`, some RAMB36E1 parameter modes aren't generating valid encodin…
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With the ongoing effort on adding the FPGA interchange support to VPR, some additional data would be required in the device resources ([VTR docs](https://docs.verilogtorouting.org/en/latest/arch/refer…
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The largest US+ fabrics like the VU19P fail when writing the FPGA interchange device database because the flat node storage model in the FPGA interchange device database is too memory intensive.
Th…