chipsalliance fpga-interchange-schema issues

chipsalliance / fpga-interchange-schema

https://fpga-interchange-schema.readthedocs.io/

Apache License 2.0

48 stars 20 forks source link

issues

Newest

Newest Most commented Recently updated Oldest Least commented Least recently updated

Adding stub nodes for partially routed nets

#78 clavin-xlnx closed 2 years ago
0
docs: theme s/SymbiFlow/F4PGA/

#77 umarcor closed 2 years ago
0
List BEL bindings available for cell instances of macro expansions

#76 kboronski-ant opened 2 years ago
2
🔄 Synced file(s) with SymbiFlow/symbiflow-common-config

#75 common-config-bot opened 2 years ago
0
docs: conf cleanup, add logo and favicon, use _static

#74 umarcor closed 2 years ago
0
readme: update python-fpga-interchange URL; update license headers

#73 umarcor closed 2 years ago
1
docs/conf: update theme colors

#72 umarcor closed 2 years ago
1
Docs: rename to CHIPS

#71 kgugala closed 2 years ago
0
Name change on Interchange Docs?

#70 clavin-xlnx closed 2 years ago
3
Fix annotations in DeviceResources

#69 mtdudek closed 2 years ago
0
ASIC diagrams are wobbly?

#68 mithro closed 2 years ago
1
Tile corners and annotations fixes

#67 mtdudek closed 2 years ago
0
Add Bel pins clocking information

#66 acomodi opened 2 years ago
1
Fix Licenses

#65 kgugala closed 2 years ago
0
docs: remove file prefix from env

#64 kgugala closed 2 years ago
1
ReadTheDocs failing due to issue with conda?

#63 mithro closed 2 years ago
1
fix transposed letters in github link

#62 elms closed 2 years ago
3
PinDelay should use StringIdx for bel pins, not BelPinIdx

#61 gatecat opened 3 years ago
0
Get Conns for Wires

#60 reillymck opened 3 years ago
0
Add license check GH Action

#59 tmichalak closed 2 years ago
0
device: Document constant bel pin rules

#58 gatecat closed 3 years ago
0
interchange: Add sub-tiles, needed for Nexus FASM generation

#57 gatecat closed 3 years ago
3
schema: physical: add site information to physicalPip

#56 acomodi closed 3 years ago
0
Choice of bel pins for a cell pin

#55 gatecat opened 3 years ago
1
RFC: Split wire/node mapping into a new schema

#54 gatecat opened 3 years ago
0
"Inverting routing BELs" duplicated

#53 mithro opened 3 years ago
0
docs: Add a diagram showing legal/illegal site pip usage

#52 gatecat closed 3 years ago
0
docs: Clarify correct usage of site PIPs

#51 gatecat closed 3 years ago
0
Site PIP usage contract

#50 gatecat closed 3 years ago
1
Capnp Schema File Structure?

#49 reillymck closed 3 years ago
2
Multi-output routing bels

#48 gatecat opened 3 years ago
0
Site PIPs with side effects

#47 gatecat opened 3 years ago
4
Inconsistent use of Text vs StringIdx

#46 gatecat opened 3 years ago
5
WIP: interchange: add BELs chain support

#45 kowalewskijan closed 1 month ago
1
Macro (and similar) placement constraints

#44 gatecat opened 3 years ago
2
Add a documented requirement for primLibs library names

#43 gatecat closed 3 years ago
0
Add parameter mapping rules for macros

#42 gatecat closed 3 years ago
1
Macro parameter mapping

#41 gatecat closed 3 years ago
13
Allow macro expansions conditional on parameter match

#40 gatecat closed 3 years ago
0
WIP: Import background & philosophy information into the documentation.

#39 mithro opened 3 years ago
5
device: add timing delay specification

#38 acomodi closed 3 years ago
3
Add badges to the README.

#37 mithro opened 3 years ago
0
Clean up the options.

#36 mithro closed 3 years ago
0
Add specification of default cell pin values

#35 gatecat closed 3 years ago
17
UltraScale clock routing

#34 gatecat opened 3 years ago
0
Adding Sphinx documentation generation for the docs.

#33 mithro closed 3 years ago
0
Expensive wire to node mapping

#32 acomodi opened 3 years ago
1
Add Wire types and categories

#31 gatecat closed 3 years ago
2
Add license checking github action

#30 mithro closed 2 years ago
1
Need simple MUX2 descriptions in device resources

#29 litghost opened 3 years ago
1