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Hi @dicecco1 ,
Came across this work on SDAccel forum and read your paper, thx for open-sourcing!
After tweaking around the Makefile I am able to finish Make-ing the codes,
`Make runtest` passe…
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I'm following the [Running the "Hello World" Example](https://github.com/Xilinx/SDAccel-AWS-F1-Developer-Labs/blob/master/modules/module_01/lab_01_helloworld.md).
Everything works until Step 5.
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Hi,
when I try to make the sdaccel.mk file,I found the common.mk didn't exist.I wrote the tcl scripts，but my gcc didn't support c++11.I want to know whether the file common.mk inlcude the compile and…
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Currently there is `Build Report:` at the start of each build report, which I think prevents it from being machine-readable:
```
Build Report: {
"partName": "xcvu9p-flgb2104-2-i",
"lutSummary"…
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https://github.com/ReconfigureIO/reco-sdaccel/blob/d8282e472bfbabb79a45dc13c910bb22f42023f7/ci/test_afi_generation.sh#L21
`test_afi_generation.sh` is the script underpinning the 'test hw builds' st…
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I consider the option of memory-mapping columns to shared memory to be valuable. Such option will be triggered if specific metadata are supplied. Given that many data frames backed by arrow are used f…
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Hi, when you open Vivado HLS project (Vivado 2020, if it matters), you can add port…
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It makes sense that the execution does not work when no AWSXCLBIN nor XCLBIN is found, but, in my case, this situation causes a segfault on the call to `cl::Program`, which is difficult to diagnose.
…
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I use AWS EC2 f1 instance to run gemx. With (this AMI)[https://aws.amazon.com/marketplace/pp/B06VVYBLZZ]
however after I compile the gemm_kernel.h into gemm.xclbin and upload it to AWS to create AFI,…
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To use multiple banks/controlers in the DDR to enable simultaneous reads/writes, what should I make changes of the SW/HW actions in the CAPI SNAP. I am thinking to add another DDR port beside the foll…