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Dear Contributors,
When I tried to create the virtual env following your instructions, I got the following problem:
yanjunliu@Yanjuns-MacBook-Pro 3DSC % conda env create -f ./environment.yaml --…
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### Description of the Bug
supercons don't actually have the 4x amperage buff on the latest release server pack
### Reproduction
Run the latest server, e.g. supercons will overamp at their old ampe…
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Feature request to add functions to search for jtag pins for unknown pinouts. If this feature was added, it would be a must have tool.
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Do you have a full BOM?
Would love to look into possible replacement screens. Some specs and the drivers IC would be great.
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This ticket is a request for comments and collection of the discussions I've had on the Discord about this little project of mine.
I've been building an XYZ scanning microscope, using a Raspberry P…
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The 'Thermal shield' is not shown on the Poloidal cross-section but is shown in the toroidal cross-section.
This image shows there is a grey line between the inboard blanket and VV in the toroidal …
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https://arxiv.org/pdf/2004.11362
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The soc verilator executable is now too slow to test riscv executables that manipulate the display.
I believe that change that caused the reduced speed is the new 96MHz PSRAM controller. (Hooray fo…
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I'm creating this issue to collect information about possible solution for a flash translation layer for CircuitPython. While the flash memories CircuitPython boards normally use have a reasonably goo…
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In GitLab by @skahn on Mar 24, 2020, 10:58
## Design description
The bucked and wedged TF design uses the CS as support structure for the TF coil. Peter Titus, PPPL ingeneer current team lead, has r…