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Is it possible to have a feature to control execution order of the testbenches? Like having short testbenches executed first and then slow ones last or something similar.
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In our company we have only a limited number of (real) Modelsim licenses. Therefore we are using the free Modelsim version which is shipped together with Quartus for most of the testing.
Since the …
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This can help us verify coherence in the multicore cache testbenches and CCE testbenches
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I think that the best way to make sure that every single Verilog file is bug-free is to create a test bench for each one. I did this for the logic gates on my old machine, but unfortunately I don't ha…
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Is Verilator support possible? With the release of Verilator 5.00x earlier this year, Verilator now supports dynamic scheduling and delay statements making it possible for Verilator to support SystemV…
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The current setup is designed to work with CocoTB testbenches. Hopefully, we can get SV test benches to work. This will likely require some rework of the caravel-sim-infrastructure.
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After looking through all documentation I still cannot find if/how it is possible to change the settings for finding testbenches.
when not finding any testbenches VUnit gives the following output, su…
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There is a major issue with the part of test.py responsible for testing the multiplexer.
[4df0a62](https://github.com/JAC-EE/tt08-SegDecode-ASIC/commit/4df0a62ccf6a4d1bc013a6502cd1fbe8a4ab66d4)
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Alright so I was thinking for if / when we want to extend our ISA we should have some sort of automated verification that we can use to test basic cases of our design. My idea is to have a set of unit…