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While working on the Analytical Placer, I generated a very basic clustering and cluster placement. The quality of both of these was meant to be low as this is mainly just a PoC flow through VPR. These…
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### Description
Hello! While writing a custom step I'm facing the challenge to inject custom Verilog into the flow.
By this I mean the ability to add new files to the `VERILOG_FILES` variable. Unf…
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I tried naming one of my signals "dist", but Yosys failed to parse the resulting file.
Looking at its source code it uses the SystemVerilog reserved word list, even when parsing regular Verilog: ht…
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Clearly, it's been a massive pain manually regex'ing my way through Verilog source code and it only works for simplistic codebases that are pretty idealistic.
Instead, further research is required …
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APIO is a great utility and I use it frequently for testing my Verilog designs.
Are there any plans to support SystemVerilog?
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### What's hard to do? (limit 100 words)
Currently when choosing between the DSLX interpreter, the IR interpreter, the JIT or a Verilog simulator to run a set of DSLX tests: developers have to go thr…
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There are times when I need to unit test a mix of VHDL and Verilog.
Including VHDL using Verilog package which references VHDL package for types and constants.
Or Verilog code referencing VHDL packa…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched the [documentation](https://chipyard.readthedocs.io/)
### Feature…
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I need to use RFuzz on Verilog and know you all built out a way to do that. Are there instructions on how to run this capability?
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P4's slicing syntax is derived from Verilog, using expressions like:
- `foo[7:0]` -- extract the bottom 8 bits of foo
- `bar[31:24]` -- extract 8 bits bar (3rd byte from lsb)
As with Verilog, t…