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LiamSkirrow
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verilogtree
Print out the modular hierarchy of a Verilog design
MIT License
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Consider an overhaul instead using parser generators
#62
LiamSkirrow
opened
2 months ago
1
Falsely detecting module instantiation on 'else if('
#61
LiamSkirrow
opened
9 months ago
0
Create v0.1.0 tag
#60
LiamSkirrow
opened
10 months ago
0
Support of all Verilog syntax
#59
LiamSkirrow
opened
10 months ago
0
Add an install.sh script
#58
LiamSkirrow
closed
10 months ago
0
11 handle newlines in modules
#57
LiamSkirrow
closed
10 months ago
0
55 revamp makefile to be more efficient and generic
#56
LiamSkirrow
closed
11 months ago
0
Revamp Makefile to be more efficient and generic
#55
LiamSkirrow
closed
11 months ago
0
Add the -T/--top argument to set top level module manually
#54
LiamSkirrow
closed
11 months ago
0
25 test infrastructure
#53
LiamSkirrow
closed
11 months ago
0
Select an appropriate open source license
#52
LiamSkirrow
closed
10 months ago
1
Remove v0.1.0 TODOs and FIXMEs from the code
#51
LiamSkirrow
opened
11 months ago
1
GUI Mode
#50
LiamSkirrow
opened
11 months ago
0
Interactive mode
#49
LiamSkirrow
opened
11 months ago
0
add max hierarchy depth as an argument
#48
LiamSkirrow
closed
11 months ago
1
Create a specialised C++ parsing submodule
#47
LiamSkirrow
opened
11 months ago
0
ignore comments
#46
LiamSkirrow
opened
11 months ago
3
Include argument to set root node
#45
LiamSkirrow
closed
11 months ago
3
Replace Verilog parsing with Verilator
#44
LiamSkirrow
opened
1 year ago
1
Error message include missing module name
#43
LiamSkirrow
closed
1 year ago
0
Fix discrepancy when running with or without debug flag
#42
LiamSkirrow
closed
1 year ago
1
Handle case where not enough files are supplied
#41
LiamSkirrow
closed
1 year ago
0
Support module instantiations inside generate statement
#40
LiamSkirrow
opened
1 year ago
1
--ignore-modules fix bad formatting
#39
LiamSkirrow
closed
11 months ago
4
Refactor the --ignore-module to lookup table
#38
LiamSkirrow
opened
1 year ago
0
Overhaul Makefile
#37
LiamSkirrow
closed
11 months ago
1
Formatting of instance name print out
#36
LiamSkirrow
opened
1 year ago
0
Create BUILD and INSTALL scripts
#35
LiamSkirrow
closed
10 months ago
1
Add variable space between module name and instance name
#34
LiamSkirrow
opened
1 year ago
0
Include -L/--level flag
#33
LiamSkirrow
closed
1 year ago
0
Add a --find argument
#32
LiamSkirrow
opened
1 year ago
0
Spruce up README, make more complete and readable
#31
LiamSkirrow
closed
10 months ago
1
man page and help arg output
#30
LiamSkirrow
closed
11 months ago
1
Print out all the --no-include modules at the end
#29
LiamSkirrow
closed
1 year ago
0
Handle circular hierarchy segfault
#28
LiamSkirrow
closed
1 year ago
1
Parse 'ifdefs and 'defines
#27
LiamSkirrow
opened
1 year ago
1
Handle error case where module is instantiated but not declared
#26
LiamSkirrow
closed
1 year ago
2
Test infrastructure
#25
LiamSkirrow
closed
11 months ago
2
Optionally space out lines in the output text
#24
LiamSkirrow
opened
1 year ago
0
Implement an iterative/non-recursive print out mode
#23
LiamSkirrow
opened
1 year ago
0
verilogtreeconfig config file
#22
LiamSkirrow
opened
1 year ago
0
Highlight/colour specific modules and/or instance names in tree output
#21
LiamSkirrow
opened
1 year ago
0
Optionally include instance name in tree output
#20
LiamSkirrow
closed
1 year ago
0
Assert -L value is numeric
#18
LiamSkirrow
closed
1 year ago
1
Refactor arg parse code
#17
LiamSkirrow
opened
1 year ago
0
Handle duplicate arguments
#16
LiamSkirrow
closed
1 year ago
1
Include any unsupported syntax in README
#15
LiamSkirrow
closed
10 months ago
3
Does Verilog support nested module definitions?
#14
LiamSkirrow
closed
1 year ago
1
Replace current for loops with STL iterators
#13
LiamSkirrow
opened
1 year ago
0
Include a --superdebug flag
#12
LiamSkirrow
closed
1 year ago
0
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